الصفحة الرئيسية > الدوائر المتكاملة الدوائر المتكاملة > CD4518BE

CD4518BE

Dual BCD up-counter, CMOS 3-18V, dual clock/enable, PDIP-16

4000

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جزء الشركة المصنعة ： جزء الشركة المصنعة

CD4518BE

الحزمة ： الحزمة

PDIP-16 (19.3 x 6.35 x 4.57mm, 2.54mm pitch, through-hole)

العلامة التجارية ： العلامة التجارية

فئات المنتجات:：فئات المنتجات

الدوائر المتكاملة الدوائر المتكاملة, واجهة ICs

توصيات أخرى قد تكون مهتماً بها.

SII9396SCNUC-BAR

IS43TR16256BL-125KBLI

الوصف

نظرة عامة على المنتج

The CD4518BE from Texas Instruments contains two independent synchronous BCD up-counters with clock and enable inputs, each capable of counting 0-9 in BCD in a 16-pin PDIP package.

المواصفات الرئيسية

الوظيفة	Dual BCD synchronous up-counter
Technology	CD4000B CMOS
جهد الإمداد	3V to 18V
Counter Type	BCD decade (0-9)
Count Direction	Up only
Trigger	Positive-edge on CLK (when EN=HIGH) or negative-edge on EN (when CLK=LOW)
إعادة تعيين	Asynchronous, active HIGH (MR)
الحد الأقصى لتردد الساعة	6MHz typical @ VDD=10V
درجة حرارة التشغيل	-55 درجة مئوية إلى +125 درجة مئوية
الحزمة	PDIP-16 (19.3 x 6.35mm)

الميزات

Dual BCD up-counters in one package
Two clocking options: CLK edge or EN edge
Asynchronous master reset (active HIGH)
Cascadable via Q3 output
3V-18V CMOS operation

التطبيقات

Frequency counting
Event counting (0-9 per digit)
Multi-digit BCD displays
Timing and sequencing

مقدمة المنتج:CD4518BE مقدمة المنتج

The CD4518BE from Texas Instruments contains two independent BCD (Binary-Coded Decimal) up-counters. Each counter counts from 0 to 9 in BCD (0000 to 1001) and rolls over to 0. The dual clocking scheme offers flexibility: (1) Clock on the CLK pin with EN=HIGH — counting on the rising edge of CLK. (2) Clock on the EN pin with CLK=LOW — counting on the falling edge of EN. This allows either positive-edge or negative-edge triggering. The asynchronous master reset (MR=HIGH) immediately resets all four outputs to 0 regardless of clock. For multi-digit counting, the Q3 output (MSB) of one counter connects to the CLK of the next counter: when the first counter rolls from 9 to 0, Q3 transitions from HIGH to LOW and back — a positive edge on the next counter’s CLK, incrementing the next digit. The CD4518 is simpler than the CD4029 (no up/down or binary/decade selection) but provides two counters in one 16-pin package, making it efficient for multi-digit BCD displays. The BE suffix denotes the PDIP-16 package.

مبدأ العمل:CD4518BE مبدأ العمل

Each BCD counter in the CD4518BE is a 4-bit synchronous counter that sequences through 0000, 0001, 0010, … 1001, then rolls over to 0000. The counter advances when: (a) a rising edge occurs on CLK while EN is HIGH, or (b) a falling edge occurs on EN while CLK is LOW. When neither condition is met, the counter holds its value. The MR (master reset) input is asynchronous: when MR=HIGH, all Q outputs go to 0 immediately regardless of CLK and EN states. For normal counting, MR must be LOW. The Q3 output goes HIGH at count 8 and returns LOW at count 0 (rollover), providing a carry signal for cascading. To cascade for 2-digit (0-99) counting: Q3 of counter 1 → CLK of counter 2; EN of both counters tied HIGH; MR of both tied together for simultaneous reset. For frequency division: Q1 divides clock by 2, Q2 by 4, Q3 provides a pulse every 10 clocks (decade divider). The BCD outputs (Q1-Q4) connect directly to BCD-to-7-segment decoders like CD4511 for display driving.

وصف الدبوس:CD4518BE تعريف الدبوس ووظائفه

دبوس	الاسم	النوع	الوصف
1	1CLK	المدخلات	Counter 1 clock (positive edge when 1EN=HIGH)
2	1EN	المدخلات	Counter 1 clock enable (HIGH=enable, negative edge triggers when 1CLK=LOW)
3	1Q1	المخرجات	Counter 1 output LSB
4	1Q2	المخرجات	Counter 1 output bit 2
5	1Q3	المخرجات	Counter 1 output bit 3
6	1Q4	المخرجات	Counter 1 output MSB
7	1MR	المدخلات	Counter 1 master reset (active HIGH)
8	VSS	الطاقة	أرضي
9	2MR	المدخلات	Counter 2 master reset (active HIGH)
10	2Q4	المخرجات	Counter 2 output MSB
11	2Q3	المخرجات	Counter 2 output bit 3
12	2Q2	المخرجات	Counter 2 output bit 2
13	2Q1	المخرجات	Counter 2 output LSB
14	2EN	المدخلات	Counter 2 clock enable
15	2CLK	المدخلات	Counter 2 clock
16	VDD	الطاقة	Supply (3V to 18V)

Application Scenarios:In which products and applications isCD4518BE مستعمل

2-Digit Counter (0-99): Pulses → 1CLK (1EN=HIGH); 1Q4 → 2CLK (2EN=HIGH); both MR tied together; Q1-Q4 each → CD4511 → 7-segment display
Decade Divider: Clock → 1CLK; 1Q4 output = pulse every 10 clocks; divide-by-10 frequency divider
Divide-by-100: Two CD4518 counters cascaded; 1Q4 → 2CLK; 2Q4 → 3CLK (second chip); 100 pulses per output pulse
Event Counter: Sensor pulses → 1CLK; 1EN=HIGH; 1MR=reset button; Q1-Q4 read by MCU or displayed

Alternative Models:What chips are recommended as replacements for CD4518BE

الطراز	الشركة المصنعة	الفرق الرئيسي	الحزمة	Supply
CD4518BM	TI	SOIC-16 surface-mount version with identical logic function and 3-18V range	SOIC-16	3-18V
CD4518BE	TI	Through-hole DIP version for prototyping and legacy board repair	DIP-16	3-18V
HEF4518BT	NXP	Pin-compatible CMOS version with improved ESD protection and 3-15V supply	SOIC-16	3-15V
MC144518BDR2G	أونسمي	Pin-compatible equivalent with RoHS compliance and AEC-Q100 automotive option	SOIC-16	3-18V
74HC4518D	TI/Nexperia	HC CMOS version with higher speed and 2-6V supply for modern logic systems	SOIC-16	2-6V
74HC4518N	TI/Nexperia	HC CMOS through-hole version for prototyping with 2-6V supply range	DIP-16	2-6V
74HCT4518D	نيكسبيريا	HCT version with TTL-compatible inputs for mixed 5V TTL/CMOS systems	SOIC-16	4.5-5.5V

CD4518 is the CMOS 4000-series dual bcd up counter operating over the wide 3-18V supply range. The HEF4518 (NXP) and MC144518 (onsemi) are direct pin-compatible equivalents. For higher speed at the cost of narrower voltage range, the 74HC4518 HC/HCT families offer significantly faster propagation delay and lower power consumption at 2-6V. Surface-mount versions use the BM/M suffix (SOIC); through-hole versions use the BE suffix (DIP).