The BSS123-7-F is an N-channel enhancement mode MOSFET that operates by modulating the conductivity of a channel between source and drain using an electric field applied to the gate terminal.
Enhancement Mode Operation: With no gate-source voltage applied (VGS = 0 V), the MOSFET is in the off state. There is no conductive channel between drain and source, and only a tiny leakage current (IDSS) flows. This is the normally-off characteristic of enhancement mode devices.
Channel Formation: When a positive gate-source voltage exceeding the threshold voltage (VGS(th)) is applied, the electric field attracts electrons to the semiconductor surface beneath the gate oxide, forming an inversion layer (conducting channel) between source and drain. For the BSS123-7-F, VGS(th) is typically around 1.0-1.4 V, with a maximum of 2.0 V at ID = 1 mA.
Ohmic (Linear) Region: At low VDS, the drain current is approximately proportional to VDS, and the channel behaves like a resistor with value RDS(on). The RDS(on) is 6 Ω maximum at VGS = 10 V. Higher VGS increases the channel charge density, reducing RDS(on) and increasing drain current capability.
Saturation Region: At higher VDS, the channel pinches off near the drain end, and the drain current becomes relatively independent of VDS, limited by the gate voltage. The device acts as a current source in this region.
Switching Behavior: The MOSFET is voltage-driven and requires virtually no steady-state gate current (only the gate leakage current, typically less than 100 nA). The switching speed is determined by the time required to charge and discharge the input capacitance (Ciss = 60 pF max) through the gate driver impedance. The low Ciss enables fast turn-on and turn-off transitions, making the device suitable for high-frequency switching applications.
Trench Technology: The BSS123-7-F uses trench MOSFET technology, where the gate structure is formed vertically in a trench etched into the silicon. This approach reduces cell size and increases channel density per unit area, achieving lower RDS(on) for a given die size compared to planar MOSFET construction.