AON7410

The AON7410 from Alpha & Omega Semiconductor is a 30 V N-channel enhancement-mode power MOSFET in a thermally enhanced DFN 3x3A-8L package with exposed pad. The device uses advanced trench technology to deliver excellent RDS(on) with low gate charge, making it well-suited for DC-DC converter and load switch applications.

With 20 mOhm maximum RDS(on) at VGS = 10 V (26 mOhm at 4.5 V) and 24 A continuous drain current, the AON7410 provides high current handling in a compact 9 mm2 footprint. The 9.8 nC typical gate charge at 10 V enables efficient switching at frequencies up to several hundred kHz with minimal gate-drive loss.

The DFN 3x3A-8L package features a large exposed thermal pad on the bottom that provides a low-impedance thermal path to the PCB. With RthJA of approximately 50-60C/W on a 1 in2 FR4 board with 2 oz copper, the package can dissipate up to 20 W at case temperatures up to 25C, or 3.1 W in free air at 25C ambient.

The device is 100% UIS (Unclamped Inductive Switching) tested and 100% Rg tested, ensuring reliable avalanche energy handling and consistent gate resistance for predictable switching behavior. The 1.4-2.5 V threshold voltage range provides logic-level drive capability from 2.5 V and above.

The AON7410 is halogen-free, antimony-free, and RoHS compliant. It is qualified for industrial applications with a maximum junction temperature of 150C. Tape-and-reel packaging contains 5000 units per reel for automated SMT assembly.

**N-Channel Trench MOSFET:** The AON7410 uses trench gate technology where vertical trenches are etched into the silicon and the gate electrode is formed inside these trenches. This creates a large channel width per unit die area, achieving the low 20 mOhm RDS(on). Current flows vertically from source (top) through the channel to drain (bottom/exposed pad).

**Enhancement-Mode Operation:** With VGS below the threshold (1.4-2.5 V), no channel forms and the device is off. When VGS exceeds VGS(th), an inversion layer forms under the gate oxide, creating a conductive N-type channel. RDS(on) decreases with increasing VGS as the channel becomes more enhanced.

**DFN 3x3A-8L Pinout:** The 8-pin DFN package dedicates pins 1-3 to source, pin 4 to gate, and pins 5-8 to drain (plus exposed pad = drain). This multi-pin drain/source configuration minimizes package parasitic inductance and resistance. The exposed pad serves as both the primary thermal path and the drain connection.

**Avalanche Rating:** The 100% UIS testing guarantees each device can safely absorb inductive energy during unclamped switching events. The device is rated for 17 A avalanche current and 14 mJ single-pulse avalanche energy.