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74LVC1G157GV

Single 2-input MUX, 1.65-5.5V, Schmitt, TSOP6

18500

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Manufacturer Part：

74LVC1G157GV

Package：

TSOP6 / SOT457 / SC-74 (3.1 x 1.7 x 1.0 mm)

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Description

Product Overview

The 74LVC1G157GV is a Nexperia single 2-input multiplexer with 1.65V to 5.5V supply, Schmitt-trigger inputs, ±24mA output drive, and IOFF partial power-down support. Packaged in TSOP6 (SOT457/SC-74), -40°C to +125°C.

Key Specifications

Supply Voltage 1.65 V to 5.5 V
Propagation Delay 2.2 ns typical
Output Drive ±24 mA @ 3.0V
Inputs Overvoltage tolerant to 5.5V
ESD HBM >2000V, CDM >1000V
Package TSOP6 (SOT457)

Features

  • Single 2-input multiplexer (1-bit MUX)
  • 1.65V to 5.5V wide supply range
  • Schmitt-trigger inputs for noise immunity
  • 5.5V overvoltage tolerant inputs
  • IOFF circuitry for partial power-down
  • ±24mA output drive at 3.0V

Applications

  • Signal routing and selection
  • 3.3V/5V mixed-voltage interfacing
  • Clock multiplexing
  • Board-level signal steering

The 74LVC1G157GV is a Nexperia single 2-input multiplexer in a TSOP6 (SOT457/SC-74) package. The device selects one of two data inputs (I0 or I1) under control of a common select input (S), presenting the selected data at the output (Y) in true (non-inverted) form. The 1.65V to 5.5V supply range allows the device to operate at any common logic voltage, and the overvoltage-tolerant inputs accept signals up to 5.5V regardless of VCC, enabling use as a level translator in mixed 3.3V/5V environments. Schmitt-trigger action at all inputs provides high noise immunity and tolerance for slow input rise and fall times. The ±24mA output drive at 3.0V can directly interface with multiple TTL or CMOS loads. The IOFF circuitry disables the output when VCC = 0V, preventing damaging backflow current in partial power-down applications such as hot-swap and standby modes. The 2.2ns typical propagation delay supports high-speed signal routing. The device complies with JEDEC standards for all supply voltage ranges and provides ESD protection exceeding 2000V HBM and 1000V CDM.

The 74LVC1G157 is a combinatorial logic device implementing the boolean function Y = (I0 AND /S) OR (I1 AND S). When the select input S is LOW, the I0 input is routed to the output Y; when S is HIGH, the I1 input is routed to the output. The Schmitt-trigger input buffers convert slowly-changing or noisy input signals into clean digital levels with hysteresis, preventing oscillation and reducing susceptibility to noise. The output buffer provides ±24mA drive capability. The IOFF circuit consists of a series switch between the output driver and the output pin that opens when VCC drops to 0V, preventing current flow from the output pin through the internal ESD diodes to VCC. The overvoltage-tolerant input structure uses a separated input NMOS gate that can withstand voltages up to 5.5V even when VCC is lower, enabling level translation without additional components.

Pin Mnemonic Description
1 I1 Data input from source 1
2 GND Ground (0V)
3 I0 Data input from source 0
4 Y Multiplexer output
5 VCC Supply voltage (1.65-5.5V)
6 S Common data select input
  • Clock source selection between crystal oscillator and external clock using S pin for dynamic switching
  • 3.3V to 5V signal level translation using overvoltage-tolerant inputs in mixed-voltage system
  • Debug/test signal injection mux selecting between functional and test data paths
  • Hot-swap board signal steering with IOFF preventing backflow when card is unpowered
Model Manufacturer Key Difference
74LVC1G157GW Nexperia TSSOP6 (SOT363) package
74LVC1G157GM Nexperia XSON6 leadless package
74LVC1G157GV-Q100 Nexperia Automotive qualified
SN74LVC1G157DCKR TI SC-70-6 package equivalent
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