UCC27511DBVR

The UCC27511DBVR from Texas Instruments is a single-channel, high-speed, low-side gate driver designed to efficiently drive MOSFET, IGBT, and GaN FET power switches in switch-mode power supplies, motor drives, and other power conversion applications.

The UCC27511 is part of the UCC2751x family that includes the UCC27511 (split output, asymmetric drive) and UCC27512 (single output, symmetric drive). The UCC27511 variant is optimized for applications that require independent control of turn-on and turn-off speeds, which is achieved through its unique split output configuration.

The split output configuration provides two output pins: OUTH (source) and OUTL (sink). This allows the designer to connect different gate resistors to each pin, independently controlling the turn-on and turn-off slew rates of the power switch. A smaller turn-on resistor (connected to OUTH) enables fast turn-on for low switching losses, while a larger turn-off resistor (connected to OUTL) slows down turn-off to prevent excessive voltage overshoot caused by parasitic inductance. This split-output approach saves one external diode compared to the traditional method of using a gate resistor with a parallel diode for asymmetric drive.

The 4 A source / 8 A sink asymmetric drive is specifically designed to combat the Miller turn-on effect in bridge and half-bridge configurations. During the turn-off of the high-side switch, the rapidly falling switch node voltage couples through the Miller capacitance (CGD) of the low-side switch, injecting a displacement current that can momentarily turn on the low-side switch, causing shoot-through current. The strong 8 A sink capability of the UCC27511 quickly pulls the gate voltage below the Miller plateau, preventing this parasitic turn-on.

The 13 ns typical propagation delay is among the fastest in the industry for gate driver ICs, enabling high-frequency switching (100 kHz to several MHz) with minimal pulse transmission distortion. The fast 9 ns rise time and 7 ns fall time ensure rapid switching of the power transistor, minimizing switching losses.

The dual-input design (IN+ and IN-) is a standout feature that provides maximum flexibility. The same device can be configured as a non-inverting driver (signal applied to IN+, IN- tied low), an inverting driver (signal applied to IN-, IN+ tied high), or used with both inputs for logic combining. The unused input pin can also serve as an enable/disable function. Internal pull-up and pull-down resistors ensure the output is held low when input pins are floating, providing a fail-safe condition.

The TTL/CMOS compatible input thresholds (independent of VDD) allow the UCC27511 to be directly driven by 3.3 V or 5 V logic from MCUs and DSPs, regardless of the gate driver supply voltage. The wide hysteresis between the high and low thresholds (approximately 1 V) provides excellent noise immunity in the noisy environment typical of power electronics.

The wide -40 to 140 degrees C operating temperature range exceeds most gate driver ICs (typically rated to 125 or 150 degrees C), making the UCC27511 suitable for demanding automotive and industrial environments where high ambient temperatures are common.

The SOT-23-6 package is the smallest available package for a gate driver with this level of performance, making it ideal for space-constrained applications. The 6 pins accommodate the dual inputs, split outputs, VDD, and GND without compromising functionality.

The UCC27511DBVR operates as a high-speed buffer amplifier between a low-power PWM controller and a high-power switching transistor (MOSFET, IGBT, or GaN FET).

Input Stage: The UCC27511 features a dual-input architecture with IN+ (non-inverting) and IN- (inverting) pins. The output state is determined by the logic AND of the two inputs: the output is HIGH when IN+ is HIGH and IN- is LOW, and the output is LOW in all other input combinations. This truth table allows the device to function as either an inverting or non-inverting driver, depending on which input receives the PWM signal and how the other input is biased. Internal pull-up (IN-) and pull-down (IN+) resistors ensure the output is held LOW when inputs are floating, providing a safe default state.

Input Threshold Logic: The input threshold levels are based on TTL/CMOS-compatible low-voltage logic and are fixed at approximately 1.2 V (LOW) and 2.2 V (HIGH), regardless of the VDD supply voltage. This means the UCC27511 can be driven directly from 3.3 V or 5 V logic signals even when VDD is 12 V or 15 V. The approximately 1 V hysteresis between the high and low thresholds provides excellent noise immunity, preventing false switching due to ground bounce or EMI coupling.

Output Stage: The UCC27511 features a split output configuration with OUTH and OUTL pins. The OUTH pin sources current through a hybrid pull-up structure consisting of a P-channel MOSFET in parallel with an N-channel MOSFET. The N-channel MOSFET is briefly turned on during the output rising edge to provide a boost in peak source current (the Gate Voltage Boost feature), reducing the effective source resistance during the Miller plateau region. The OUTL pin sinks current through an N-channel MOSFET pull-down structure with very low on-resistance. This asymmetric design provides 4 A peak source and 8 A peak sink capability.

Split Output Operation: The OUTH pin connects to the power switch gate through a turn-on gate resistor (RGO), and the OUTL pin connects through a turn-off gate resistor (RGOFF). During turn-on, OUTH drives current through RGO to charge the gate capacitance. During turn-off, OUTL sinks current through RGOFF to discharge the gate. By choosing RGO smaller than RGOFF, the turn-on can be fast (low switching loss) while the turn-off is slower (reducing voltage overshoot). Alternatively, choosing RGOFF smaller than RGO provides fast turn-off with slower turn-on.

UVLO Protection: The undervoltage lockout circuit monitors the VDD supply voltage. When VDD is below the UVLO threshold (approximately 4.5 V), the output is held LOW regardless of the input signals. This ensures that the power switch is not driven with insufficient gate voltage, which could cause it to operate in the linear region and overheat. The UVLO has approximately 350 mV of hysteresis to prevent chattering near the threshold.

Propagation Delay: The internal signal path from input to output is optimized for minimum propagation delay. The typical delay is 13 ns at VDD = 12 V, with very little variation across the VDD and temperature range (less than 20 ns under all conditions). This fast and consistent propagation delay minimizes pulse width distortion and dead-time requirements in bridge converter applications.

Shoot-Through Prevention: The output stage design inherently minimizes shoot-through current (simultaneous conduction of the pull-up and pull-down structures). The anti-shoot-through circuitry ensures a minimum dead time between the OUTH turning off and OUTL turning on (and vice versa), preventing excessive supply current spikes during output transitions.

Driving GaN FETs: The UCC27511 is particularly well-suited for driving enhancement-mode GaN FETs, which require low gate drive voltages (5-6 V), very fast switching speeds, and minimal parasitic inductance in the gate loop. The SOT-23-6 package has very low parasitic inductance, and the split output allows a 0 Ohm turn-on resistor (OUTH directly to gate) with a slightly larger turn-off resistor (OUTL through 1-2 Ohm) for optimal GaN switching performance.