TUSB9261PVP

The TUSB9261PVP from Texas Instruments is a fully integrated USB 3.0 to SATA bridge controller that enables the design of external hard disk drives, solid-state drives, and optical drive enclosures with a single-chip solution. It bridges the SuperSpeed USB 3.0 bus (5 Gbps) to the Serial ATA bus (up to 3 Gbps, SATA Gen2), providing the hardware and firmware to implement a complete mass storage device.

The TUSB9261 is built around an integrated ARM Cortex-M3 microcontroller core that runs the bridge firmware. The firmware implements the USB Attached SCSI Protocol (UASP), which provides significantly higher throughput than the legacy USB Mass Storage Class Bulk-Only Transport (BOT) protocol. UASP eliminates the command queueing bottleneck of BOT by allowing multiple commands to be outstanding simultaneously, enabling the drive to process commands out of order and overlap data transfers. With UASP and USB 3.0, the TUSB9261 can achieve sustained data transfer rates exceeding 200 MB/s with a SATA Gen2 SSD, compared to approximately 40 MB/s with BOT over USB 2.0.

The USB interface supports SuperSpeed (5 Gbps), High-Speed (480 Mbps), and Full-Speed (12 Mbps) signaling, providing backward compatibility with USB 2.0 and USB 1.1 hosts. The integrated SuperSpeed transceiver eliminates the need for an external USB 3.0 PHY. The best-in-class adaptive equalizer in the USB receiver provides superior jitter tolerance, enabling reliable operation with longer cables and lower-quality signal paths.

The SATA interface supports all Gen1 (1.5 Gbps) and Gen2 (3.0 Gbps) signaling rates, as well as the Gen1m and Gen2m spread-spectrum signaling modes. It is compatible with the ATA/ATAPI-8 specification, supporting HDDs, SSDs, optical drives (CD/DVD/Blu-ray), and other SATA mass-storage devices.

The firmware is stored in an external SPI EEPROM and loaded into internal SRAM at power-up. This allows the firmware to be updated in the field via USB using a TI-provided application, enabling bug fixes and feature additions without hardware changes. The SPI interface also provides two additional chip selects (SPI_CS1 and SPI_CS2) that can be used to connect peripheral devices such as a second EEPROM, a security chip, or a configuration register.

Up to 12 GPIO pins provide flexibility for product differentiation. Two of the GPIO pins include PWM functionality that can drive activity LEDs with configurable blink rates, eliminating the need for external LED driver circuitry. The remaining GPIOs can be used for product-specific functions such as write-protect switches, power control, or configuration strapping.

The UART debug interface provides a serial console for development and troubleshooting. The JTAG interface supports IEEE 1149.1 boundary scan for manufacturing test and IEEE 1149.6 for AC testing of the differential USB and SATA signals.

The integrated spread spectrum clock generation (SSCG) allows operation from a single low-cost 40 MHz crystal or clock oscillator, reducing BOM cost. The SSCG modulates the clock frequency slightly to spread the EMI energy across a wider bandwidth, helping the product pass FCC/CISPR emissions testing.

The PVP suffix denotes the HTQFP-64 (Heat-sink Thin Quad Flat Pack) package with 0.5 mm pitch. The device requires two supply voltages: 1.1 V (core and USB/SATA PHY) and 3.3 V (I/O). An external voltage regulator is typically used to generate the 1.1 V supply from the 3.3 V or 5 V input.

Important note: The default TI firmware and reference design have the SATA TXP/TXM signals swapped for ease of PCB routing. Designers using the TI default firmware must review the reference design in the TUSB9261 DEMO User’s Guide (SLLU139) for proper SATA connection.

The TUSB9261PVP operates as a USB 3.0 to SATA protocol bridge with an integrated ARM Cortex-M3 controller managing all data transfers and protocol conversion.

ARM Cortex-M3 Core: The on-chip Cortex-M3 core runs the bridge firmware that handles all USB and SATA protocol processing, command translation, data management, and error handling. The firmware is loaded from an external SPI EEPROM into internal SRAM at power-up. The firmware implements multiple USB device class interfaces simultaneously: UASP (for high-performance data transfer), BOT (for legacy compatibility), and HID (for firmware updates and device configuration).

USB 3.0 SuperSpeed Operation: The USB 3.0 interface operates at 5 Gbps using two differential signal pairs: one for transmit (USB_SSTXP/M) and one for receive (USB_SSRXP/M). The USB 3.0 protocol uses separate unidirectional paths for upstream and downstream data, enabling simultaneous bidirectional communication. The TUSB9261 implements the USB Mass Storage Device (MSD) function using UASP, which supports up to 65535 queued commands per LUN with command completion notification. The adaptive equalizer in the receiver automatically adjusts to compensate for signal degradation from cable loss, ensuring reliable data reception.

USB 2.0 Backward Compatibility: In addition to SuperSpeed, the TUSB9261 supports USB 2.0 High-Speed (480 Mbps) and Full-Speed (12 Mbps) operation through the USB_DP/DM pins. When connected to a USB 2.0 host, the device automatically falls back to High-Speed or Full-Speed operation using the BOT protocol (UASP is not supported over USB 2.0). This backward compatibility is automatic and requires no firmware intervention.

SATA Operation: The SATA interface operates at Gen1 (1.5 Gbps) or Gen2 (3.0 Gbps) using differential transmit (SATA_TXP/M) and receive (SATA_RXP/M) pairs. The TUSB9261 implements the Serial ATA protocol including FIS (Frame Information Structure) generation and parsing, DMA setup, and data management for both read and write operations. The SATA link speed is auto-negotiated with the connected device.

Protocol Translation: The firmware translates USB mass storage commands (SCSI commands encapsulated in UASP or BOT) to SATA/ATA commands. For example, a SCSI READ(10) command from the USB host is translated to an ATA READ DMA command on the SATA bus. The firmware manages the data buffers, handles command queuing, and manages error recovery between the two buses.

Clock Architecture: The 40 MHz reference clock is provided by an external crystal or oscillator connected to the XI/XO pins. The FREQSEL[1:0] pins are strapped to configure the internal PLL multiplier for the correct input frequency (11 = 40 MHz). The PLL generates the high-frequency clocks needed for the USB 3.0 PHY (5 GHz), the SATA PHY (1.5 or 3 GHz), and the Cortex-M3 core. The spread spectrum clock generation (SSCG) modulates the PLL output frequency slightly to reduce EMI peaks.

Power Management: The TUSB9261 requires two supply voltages: 1.1 V (core, USB/SATA PHY) and 3.3 V (I/O, analog). The 1.1 V supply can be generated from the 3.3 V or 5 V input using an external LDO or switching regulator. The USB_VBUS pin detects USB bus power and can be used to control the external power supply. The device supports both VBUS-powered and externally-powered configurations.

SPI EEPROM Interface: The SPI interface (SPI_SCLK, SPI_DATA_IN, SPI_DATA_OUT, SPI_CS0) connects to an external EEPROM (typically 128 KB or 256 KB) that stores the firmware image. At power-up, the boot ROM loads the firmware from the EEPROM into internal SRAM. Two additional chip selects (SPI_CS1, SPI_CS2) allow peripheral expansion. The SPI clock rate is configurable up to 25 MHz.