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TPS53317ARGBT

6A DDR VTT Buck Conv, D-CAP+, 1-6Vin, VQFN-20

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Manufacturer Part：

TPS53317ARGBT

Package：

VQFN-20 (3.50 x 4.00 x 0.95 mm, 0.5mm pitch, exposed pad)

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Description

Product Overview

The TPS53317ARGBT from Texas Instruments is a 6A D-CAP+ mode synchronous step-down converter for DDR memory termination, 1-6V input, and 20-pin VQFN package.

Key Specifications

Type 6A DDR Termination Synchronous Step-Down Converter with Integrated FETs
Conversion Input Voltage 1V to 6V
V5IN Supply 4.5V to 6.5V
Output Voltage 0.6V to 2V (adjustable); tracks 1/2 VDDQ
Output Current 6A (source and sink)
Control Mode D-CAP+ (with DC compensation)
Switching Frequency 600 kHz or 1 MHz (selectable)
Quiescent Current 320 uA (typical)
Reference Voltage 0.6V, 1% accuracy
Package VQFN-20 (RGB, 3.5 x 4 mm)
Operating Temperature -40C to +85C

Features

  • 6A source and sink output current for DDR VTT
  • D-CAP+ mode for fast transient response with DC accuracy
  • External tracking of 1/2 VDDQ reference
  • Selectable 600kHz or 1MHz switching frequency
  • Auto-skip Eco-mode or forced CCM
  • Pre-bias startup capability
  • Output soft discharge
  • Integrated bootstrap switch and power-good

Applications

  • DDR/DDR2/DDR3/DDR4 VTT termination regulator
  • Low-voltage POL regulation
  • FPGA core power from 1V-6V rails

The TPS53317ARGBT from Texas Instruments is a 6A integrated-FET synchronous step-down converter specifically designed for DDR memory termination (VTT) applications in a 3.5x4mm 20-pin VQFN package. The RGB suffix denotes the VQFN-20 package, T indicates mini-reel packaging (250 units), and the A suffix indicates the automotive or extended-grade version. The device provides 6A continuous output current with both source and sink capability, which is essential for DDR VTT termination where the regulator must both supply and absorb current depending on the data bus activity. The D-CAP+ control mode adds DC compensation to the standard D-CAP architecture, providing the fast transient response of constant-on-time control while eliminating the DC offset typically associated with ripple-based regulators. The output voltage tracks an external reference (typically 1/2 VDDQ) applied to the REFIN pin, automatically maintaining the correct termination voltage for any DDR generation. The selectable 600kHz or 1MHz switching frequency allows designers to trade off efficiency and solution size. The auto-skip Eco-mode reduces switching frequency at light loads to maintain efficiency, while forced CCM is available for noise-sensitive applications.

The TPS53317ARGBT uses TI’s D-CAP+ control mode, which is an enhanced constant-on-time architecture with DC compensation. In standard D-CAP mode, the controller triggers an on-time pulse whenever the output voltage ripple dips below the reference threshold. The on-time duration is adaptively calculated to maintain the target switching frequency. The D-CAP+ enhancement adds a DC compensation circuit that measures the average difference between the output voltage and the reference, and adjusts the on-time to eliminate the DC offset inherent in pure ripple-based control. This provides the fast transient response of constant-on-time control (no error amplifier compensation limiting bandwidth) while achieving the DC accuracy of voltage-mode control. For DDR VTT applications, the REFIN pin receives an external voltage (typically 1/2 VDDQ from a resistor divider on the VDDQ rail), and the converter regulates its output to match this reference. The source-and-sink capability is implemented with a bidirectional output stage: when the VTT bus is being pulled high by the DDR termination resistors, the converter sinks current (low-side MOSFET on); when the bus is being pulled low, the converter sources current (high-side MOSFET on). The integrated MOSFETs are optimized for low duty-cycle operation with the 1V to 6V input range typical of DDR power architectures.

Pin Group Name Type Function
Power VIN Power Conversion input (1-6V)
Power V5IN Power 5V bias supply (4.5-6.5V)
Power SW Output Switch node (inductor connection)
Power GND, PGND Power Ground connections
Control VOUT/FB Input Output voltage feedback
Control REFIN Input External reference input (tracks 1/2 VDDQ)
Control EN Input Enable (HIGH=on)
Control MODE Input Mode/skip/CCM/frequency select
Control PGOOD Output Power-good (open-drain)
Bootstrap BST I/O Bootstrap capacitor for HS driver
  • DDR3 VTT termination regulator tracking 1/2 x 1.5V VDDQ = 0.75V with 6A source/sink capability and D-CAP+ fast transient response for high-speed data bus termination
  • 1.2V to 0.6V FPGA auxiliary rail POL converter at 3A with 600kHz switching and auto-skip Eco-mode for idle-power savings
  • DDR4 VTT at 0.6V (1/2 x 1.2V VDDQ) with 1MHz switching for minimum inductor size and forced CCM for reduced output ripple
Manufacturer Part Number Package Notes
TI TPS53317ARGBR VQFN-20 Same, tape and reel (3000qty)
TI TPS51200DRVR SON-10 DDR VTT, lower current (2A)
TI TPS53515ARGBT VQFN-20 12A, not DDR-specific
Infineon IR3898MTRPBF PQFN-35 8A integrated FET, DDR capable
TI TPS51116RGYR VQFN-20 DDR complete VDDQ+VTT+VREF
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