TPS27081ADDCR

The TPS27081ADDCR from Texas Instruments is a high-side load switch that integrates a power P-channel MOSFET (Q1) and a control N-channel MOSFET (Q2) in a tiny 6-pin SOT-23-THIN package. It is designed for applications requiring controlled turn-on of power rails with adjustable slew rate, level-shifted logic control, and very low on-resistance. The device supports input voltages from 1.2V to 8V and can be controlled by logic signals as low as 1V, making it ideal for interfacing low-voltage microcontrollers with higher-voltage power rails.

The key innovation of the TPS27081A is its adjustable slew rate control, which allows the designer to precisely set the turn-on and turn-off ramp rates of the output voltage. This is critical in systems with large output capacitors, where uncontrolled turn-on can cause excessive inrush current that disrupts the power supply, triggers overcurrent protection, or damages connectors. By adding external resistors (R1, R2) and a capacitor (C1), the designer can set the rise time and fall time of the output voltage to any desired value, typically in the range of 100us to 10ms.

The integrated Q1/Q2 architecture provides the level-shifting function automatically. Q2 is a small N-channel MOSFET whose drain is connected to the gate of Q1 (the power PFET). When the ON/OFF pin is driven HIGH (above approximately 1V), Q2 turns on, pulling the gate of Q1 toward the R2 pin voltage (typically GND). This turns on Q1, connecting VIN to VOUT. When the ON/OFF pin is driven LOW, Q2 turns off, and the pull-up resistor R1 pulls the gate of Q1 to VIN, turning off Q1. The R1 resistor serves as both a level-shifter and a pull-up for the PFET gate. Because Q2 is referenced to the R2 pin (GND) and the ON/OFF pin can accept voltages as low as 1V, the device can be controlled by 1V logic while switching up to 8V power rails, without any external level-shifter IC.

The RDS(on) of the internal PFET varies with the gate drive voltage. At VIN=4.5V (VGS=-4.5V), RDS(on) is 32mOhm, which is very low for a MOSFET integrated into a SOT-23 package. At lower input voltages, RDS(on) increases: 44mOhm at 3V, 82mOhm at 1.8V, 155mOhm at 1.2V. This voltage-dependent RDS(on) must be considered in thermal calculations, especially at low input voltages where both the load current and the RDS(on) contribute to power dissipation.

The TPS27081A is unique among load switches in offering both adjustable slew rate and level-shifted control in a 6-pin package. Most competing load switches offer fixed slew rates (internal soft-start) and require the control logic voltage to match the supply voltage, or require a separate enable pin that is not level-shifted. The TPS27081A’s external R1/R2/C1 approach gives the designer full control over the switching behavior, at the cost of three external passive components.

The ultra-low standby leakage of 100nA typical ensures minimal battery drain when the switch is off, making the device suitable for always-on battery-powered systems. When the ON/OFF pin is LOW, Q2 is off, R1 pulls the Q1 gate to VIN, and both Q1 and Q2 are in the off state. The only leakage paths are the sub-threshold leakage of Q1 and Q2, plus the current through R1 (which can be minimized by using a large R1 value, typically 100k-1M ohm).

The TPS27081ADDCR is the tape-and-reel version (3,000 units per reel) in the DDC (SOT-23-THIN) package. The top-side marking starts with AU followed by a character designating the assembly site.

The TPS27081ADDCR operates as an integrated PFET load switch with NMOS gate control and external slew rate adjustment.

Integrated Q1/Q2 Architecture: The device contains two MOSFETs in a single package. Q1 is the main power P-channel MOSFET connected between VIN (source) and VOUT (drain). Q2 is a small N-channel MOSFET that controls the gate of Q1. The drain of Q2 is connected to the R1/C1 pin (gate of Q1), and the source of Q2 is connected to the R2 pin. The gate of Q2 is driven by the ON/OFF control input.

Turn-On Sequence: When the ON/OFF pin is driven HIGH (above approximately 1V), Q2 turns on. This creates a current path from the R1/C1 pin (Q1 gate) through Q2 to the R2 pin (GND). The current through this path is limited by the external resistor R2 (if used) and the internal RDS(on) of Q2. As current flows, the voltage at the R1/C1 pin (Q1 gate) decreases toward the R2 pin voltage. When VGS of Q1 exceeds the threshold voltage (approximately -1V), Q1 begins to turn on, and VOUT starts to rise. The rate at which VOUT rises (slew rate) is determined by how quickly the Q1 gate voltage changes, which in turn is determined by the R1-C1 time constant and the R2 current limit.

Adjustable Slew Rate: The slew rate is controlled by three external components: (1) R1 (pull-up resistor between VIN and R1/C1) – determines the turn-off speed and the steady-state gate drive; (2) R2 (resistor between R2 pin and GND) – limits the gate discharge current, controlling the turn-on slew rate; (3) C1 (capacitor between R1/C1 and VOUT) – provides feedback that makes the turn-on ramp more linear. When C1 is used, the VOUT voltage is fed back to the gate through the capacitor, creating a Miller effect that slows and linearizes the turn-on ramp. The approximate rise time is t_rise = R1 x C1 (when C1 is used) or t_rise = R1 x Ciss_Q1 (when C1 is not used), where Ciss_Q1 is the input capacitance of Q1. Typical values are R1 = 100k-1M ohm, R2 = 0-10k ohm (0 ohm for no slew rate control), and C1 = 1-100nF.

Turn-Off Sequence: When the ON/OFF pin is driven LOW, Q2 turns off. The R1 resistor then pulls the R1/C1 pin (Q1 gate) toward VIN through R1, charging the gate capacitance and turning off Q1. The turn-off time is approximately t_off = R1 x (Ciss_Q1 + C1). The R2 pin has no effect during turn-off because Q2 is off. If fast turn-off is needed, a smaller R1 value is used, but this increases the standby current through R1 (I_R1 = VIN / R1).

Level Shifting: The ON/OFF pin is referenced to the R2 pin (GND). It can accept logic levels from 1V to 8V, independent of the VIN voltage. This means a 1.8V microcontroller GPIO can control an 8V power rail without any external level-shifting circuitry. The Q2 gate threshold is approximately 0.7V, so any logic signal above 1V reliably turns on Q2. The maximum ON/OFF voltage is limited to 8V by the Q2 gate-source oxide rating.

Standby Current: When the switch is off (ON/OFF = LOW), the only current drawn from the VIN supply is the leakage through Q1 (typically < 100nA) plus the current through R1 (I = VIN / R1). For R1 = 1M ohm and VIN = 5V, the R1 current is 5uA. The total standby current is therefore dominated by the R1 choice. For ultra-low standby applications, R1 can be increased to 10M ohm or more, reducing the R1 current to sub-microamp levels, but at the cost of slower turn-off time. Power Sequencing: Multiple TPS27081A devices can be cascaded for power sequencing. The VOUT of one device can be connected (through a resistor divider) to the ON/OFF pin of the next device, ensuring that power rails turn on in the correct order. The adjustable slew rate prevents inrush current in each stage, and the level-shifted ON/OFF eliminates the need for external level shifters between different voltage domains.