STM32F072CBT6

The STM32F072CBT6 from STMicroelectronics is the flagship device of the STM32F0x2 USB line, offering the most complete peripheral set in the STM32F0 family within a compact 48-pin LQFP package. It combines an ARM Cortex-M0 core running at 48 MHz with an exceptionally rich set of communication interfaces including USB, CAN, and HDMI CEC, making it uniquely positioned for applications that require multiple wired connectivity options in a small form factor.

The STM32F072CBT6 belongs to the STM32F072xB sub-family, which features 128 KB Flash and 16 KB SRAM. The C suffix denotes a 48-pin package, the B suffix denotes 128 KB Flash, the T suffix denotes LQFP package, and the 6 suffix denotes the -40 to +85 degree C industrial temperature range. A T7 variant extends the temperature range to +105 degrees C.

The standout feature of the STM32F072 is the USB 2.0 full-speed device interface with crystal-less operation. The internal 48 MHz RC oscillator, trimmed by an automatic calibration mechanism synchronized to the USB Start-of-Frame (SOF) signal, eliminates the need for an external crystal for USB operation. This reduces BOM cost and board space significantly. The USB peripheral supports Battery Charging Detection (BCD) per the USB BC 1.2 specification and USB Link Power Management (LPM) per the USB 2.0 LPM ECN, enabling low-power USB device designs.

The CAN 2.0B interface is rare in the Cortex-M0 class and distinguishes the STM32F072 from competitors. It supports both standard (11-bit) and extended (29-bit) identifiers with three transmit mailboxes, two receive FIFOs, and loop-back/silent modes for diagnostics. This makes the STM32F072CBT6 ideal for industrial and automotive applications that require CAN bus connectivity without the cost of a Cortex-M3 or Cortex-M4 device.

The HDMI CEC (Consumer Electronics Control) interface enables the device to communicate with other CEC-enabled devices over the HDMI cable, a unique feature in this class of microcontroller. Combined with USB, this makes the STM32F072 particularly attractive for consumer electronics applications such as A/V receivers, digital TV adapters, and USB-C to HDMI adapters.

The dual-channel 12-bit DAC is another distinguishing feature. Most Cortex-M0 MCUs lack a DAC entirely, but the STM32F072 provides two independent DAC channels that can generate analog waveforms, audio signals, or control voltages. The DAC can be triggered by timers for precise waveform generation or by DMA for continuous signal generation without CPU intervention.

The capacitive sensing module supports up to 24 touch channels for touchkey, linear slider, and rotary sensor applications. This is implemented in hardware (not as a software library), reducing CPU overhead for touch sensing and enabling lower power consumption during touch detection in Stop mode.

The VDDIO2 independent I/O supply allows a subset of I/O pins to operate at a different voltage level (1.65 to 3.6 V) from the main VDD supply. This is useful for interfacing with 1.8 V logic devices without level shifters, or for mixed-voltage system designs.

Compared to the popular STM32F103C8T6 (Cortex-M3, 72 MHz, 64 KB Flash), the STM32F072CBT6 trades clock speed for a richer peripheral set at a lower price point. The STM32F072 offers USB, CAN, DAC, HDMI CEC, and capacitive sensing that the STM32F103C8T6 lacks, while the STM32F103 offers higher CPU performance and more Flash/SRAM.

The STM32F072CBT6 operates as a 32-bit ARM Cortex-M0 microcontroller with a multi-bus architecture connecting the CPU core to Flash, SRAM, and peripherals.

ARM Cortex-M0 Core: The Cortex-M0 implements the ARMv6-M architecture with a 3-stage pipeline (fetch, decode, execute). It executes a subset of the Thumb instruction set (56 instructions), providing efficient 32-bit code density using 16-bit Thumb instructions. The core includes the Nested Vectored Interrupt Controller (NVIC) supporting up to 32 maskable interrupt channels plus the non-maskable interrupt (NMI), with 4 programmable priority levels. The interrupt latency is deterministic at 15 cycles, enabling predictable real-time response.

Bus Architecture: The AHB bus matrix connects the Cortex-M0 core and the DMA controller to SRAM, Flash, and the two APB bridges (APB1 and APB2). The 7-channel DMA controller can transfer data between any combination of memory and peripherals without CPU intervention, supporting circular mode for continuous data acquisition and double-buffer mode for seamless ping-pong operation.

Flash Memory with Prefetch: The 128 KB Flash has access times that require wait states at 48 MHz (typically 1 wait state). The prefetch buffer improves linear code execution speed by fetching the next instruction ahead of the current one. The Flash also supports read-out protection (RDP) at Level 0 (no protection), Level 1 (debug access disabled, JTAG erased on unlock), and Level 2 (permanent lock, no debug access ever).

Clock System: The flexible clock tree supports multiple clock sources: HSI (8 MHz internal RC), HSI48 (48 MHz internal RC for USB), HSE (4-32 MHz external crystal), LSI (40 kHz internal RC for IWDG and RTC), and LSE (32.768 kHz crystal for RTC). The PLL can multiply HSI or HSE up to 48 MHz for the system clock. The HSI48 oscillator is automatically trimmed using the USB SOF signal for crystal-less USB operation, achieving the required plus or minus 0.25 percent frequency accuracy for USB full-speed compliance.

USB 2.0 Full-Speed Device: The USB peripheral includes dedicated packet buffer SRAM (1 KB), a CRC generator for data integrity, and double-buffered endpoints for higher throughput. The crystal-less mode uses the HSI48 oscillator with automatic trimming synchronized to the USB host SOF packets. When USB is not connected, the HSI48 can still be used as a 48 MHz system clock source (plus or minus 1 percent accuracy without USB SOF trimming). The BCD feature detects the charger type (SDP, CDP, DCP) for battery charging applications. The LPM support enables the device to enter L1 (sleep) state during USB idle periods, reducing USB power consumption.

DAC Operation: The two 12-bit DAC channels convert digital values to analog voltages with 8 us settling time. Each DAC has an output buffer that can drive external loads. The DAC output can be triggered by timer events for synchronized waveform generation, or by software for on-demand updates. DMA can supply continuous sample data to the DAC for audio or waveform generation without CPU overhead.

Capacitive Sensing: The hardware touch sensing module scans up to 24 channels autonomously, generating interrupts when a touch is detected. The module uses a charge-transfer acquisition principle, where a sensor capacitor is charged and discharged through a series resistor, and the time constant is measured to determine the capacitance change due to touch. This hardware implementation consumes less power than software-based touch scanning and can operate in Stop mode with wakeup on touch detection.

CAN 2.0B: The CAN peripheral implements the full CAN 2.0B specification with bit timing calculation, error management, and message filtering. The three transmit mailboxes allow queuing of multiple outgoing messages, while the two receive FIFOs can each hold up to three messages. The 28 filter banks provide flexible acceptance filtering, reducing CPU overhead for message handling.