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SN74LS93N

4-bit binary ripple counter, ÷2+÷8 sections, LS TTL, PDIP-14

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Manufacturer Part：

SN74LS93N

Package：

PDIP-14 (19.3 x 6.35 x 4.57mm, 2.54mm pitch, through-hole)

Brand：

Product Categories：

Integrated Circuits ICs, Interface ICs

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Description

Product Overview

The SN74LS93N from Texas Instruments is a 4-bit binary ripple counter consisting of a divide-by-2 section and a divide-by-8 section — when externally connected, it counts 0-15 in a 14-pin PDIP package.

Key Specifications

Function	4-bit binary ripple counter
Logic Family	LS (Low-power Schottky)
Supply Voltage	4.75V to 5.25V
Counter Sections	Divide-by-2 (CP0/Q0) + Divide-by-8 (CP1/Q1,Q2,Q3)
Max Count	15 (4-bit binary, 0-15)
Trigger	Negative edge (HIGH-to-LOW transition)
Reset	Asynchronous, gated AND (MR1·MR2, active HIGH)
Max Clock Frequency	25MHz typical
Propagation Delay	70ns max @ 5V
Operating Temperature	0°C to +70°C
Package	PDIP-14 (19.3 x 6.35mm)

Features

Two independent counter sections: ÷2 and ÷8
External connection Q0→CP1 creates ÷16 counter
Gated AND master reset (MR1 AND MR2 both HIGH = reset)
Negative-edge triggered
Typical power dissipation: 45mW

Applications

4-bit binary counting (0-15)
Frequency division by 2, 4, 8, 16
Time-delay circuits
Event counting

Product Introduction:SN74LS93N Product Introduction

The SN74LS93N from Texas Instruments is a 4-bit binary ripple counter consisting of two independent sections: a divide-by-2 section (clocked by CP0, output Q0) and a divide-by-8 section (clocked by CP1, outputs Q1, Q2, Q3). The two sections are NOT internally connected — the designer must externally wire Q0 to CP1 to create a full 4-bit binary counter counting 0-15 with divide-by-2, 4, 8, and 16 outputs. This separation allows flexible configurations: using only the ÷2 section, only the ÷3/÷8 section, or both together. The negative-edge triggering (counting on the HIGH-to-LOW clock transition) is standard for the 74LS90/92/93 family. The gated AND master reset requires BOTH MR1 AND MR2 to be HIGH simultaneously to reset the counter; if either is LOW, counting continues. This allows one MR input to be used as an enable while the other provides the reset function. The 74LS93 is part of the 74LS90/92/93 family: LS90 is a decade (0-9) counter, LS92 is a divide-by-12 counter, and LS93 is a 4-bit binary (0-15) counter. The N suffix denotes the PDIP-14 through-hole package.

Working Principle:SN74LS93N Working Principle

The SN74LS93N contains four JK flip-flops configured as two independent counter sections. Section 1: A single flip-flop with clock input CP0 and output Q0. It toggles on the HIGH-to-LOW transition of CP0, dividing the input frequency by 2. Section 2: Three flip-flops cascaded as a 3-bit ripple counter with clock input CP1 and outputs Q1, Q2, Q3. CP1 drives the first flip-flop (Q1), Q1 drives the second (Q2), and Q2 drives the third (Q3). The count sequence on Q3,Q2,Q1 is: 000→001→010→011→100→101→110→111→000 (divide by 8). For 4-bit binary counting: connect Q0 to CP1 externally. Input pulses on CP0; Q0 toggles at half the input rate; Q0’s HIGH-to-LOW transitions clock the ÷8 section. The full count on Q3,Q2,Q1,Q0 is 0000→0001→…→1111→0000 (0-15). Reset: when MR1 AND MR2 are both HIGH, all four flip-flops are cleared (Q0-Q3 = LOW). If either MR is LOW, the counter operates normally. The counter is negative-edge triggered throughout.

Pin Description:SN74LS93N Pin Definition and Functions

Pin	Name	Type	Description
1	CP1	Input	Clock input for ÷8 section (negative edge)
2	MR1	Input	Master reset 1 (active HIGH, AND-gated with MR2)
3	MR2	Input	Master reset 2 (active HIGH, AND-gated with MR1)
4	NC	—	No connection
5	VCC	Power	Supply (5V)
6	MR1*	Input	Master reset 1 (duplicate, connect together)
7	MR2*	Input	Master reset 2 (duplicate, connect together)
8	Q2	Output	Counter output bit 2
9	Q1	Output	Counter output bit 1
10	Q3	Output	Counter output bit 3 (MSB)
11	Q0	Output	Counter output bit 0 (LSB, ÷2 section)
12	GND	Power	Ground
13	NC	—	No connection
14	CP0	Input	Clock input for ÷2 section (negative edge)

Application Scenarios:In which products and applications isSN74LS93N used

4-Bit Binary Counter (0-15): Q0 → CP1 (external wire); input pulses → CP0; MR1 and MR2 tied together; Q0-Q3 count 0-15; divide by 2,4,8,16
Independent ÷2 and ÷8: Two separate clocks: CP0 drives Q0 (÷2); CP1 drives Q1-Q3 (÷8); no external connection needed
Frequency Divider: CP0 input; Q0=÷2, Q1=÷4, Q2=÷8, Q3=÷16 (with Q0→CP1 connected)
Controlled Reset: MR1 tied HIGH; MR2 = enable signal; counter runs when MR2=LOW, resets when MR2=HIGH; one MR as gate, other as reset

Alternative Models:What chips are recommended as replacements for SN74LS93N

Model	Manufacturer	Key Difference	Package	Supply
74LS93N	TI/Nexperia	Original TTL version with 5V-only supply, typical propagation delay 10-15ns	DIP-14	5V TTL
74LS93D	TI/Nexperia	Surface-mount SOIC version of LS with identical logic function	SOIC-14	5V TTL
74HC93D	TI/Nexperia	CMOS version with wide 2-6V supply range, lower power consumption and higher noise immunity	SOIC-14	2-6V CMOS
74HC93N	TI/Nexperia	Through-hole DIP version of HC family for prototyping and repair	DIP-14	2-6V CMOS
74HCT93D	TI/Nexperia	CMOS with TTL-compatible input levels, ideal for mixing with LS devices at 5V	SOIC-14	4.5-5.5V TTL-in
74HCT93N	TI/Nexperia	Through-hole DIP version of HCT family for prototyping and repair	DIP-14	4.5-5.5V TTL-in

The 7493 is a 4-Bit Binary Ripple Counter. Family variants span from the original LS TTL (5V only) to modern LVC/AUP (down to 0.8V). HC and HCT versions offer 2-6V CMOS operation with HCT providing TTL-compatible input thresholds for mixed 5V systems. CD4000-series equivalents offer the widest 3-18V supply range at the cost of lower switching speed. DIP packages (N suffix) are through-hole; SOIC (D suffix) and TSSOP are surface-mount.