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SN74LS75N

4-bit transparent latch, dual enables, complementary outputs, LS TTL, PDIP-16

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Manufacturer Part：

SN74LS75N

Package：

PDIP-16 (19.3 x 6.35 x 4.57mm, 2.54mm pitch, through-hole)

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Description

Product Overview

The SN74LS75N from Texas Instruments is a 4-bit bistable transparent latch — the TTL counterpart of the CD4042, providing four D-type latches with complementary outputs in a 16-pin PDIP package.

Key Specifications

Function 4-bit bistable transparent latch
Logic Family LS (Low-power Schottky)
Supply Voltage 4.75V to 5.25V
Latches 4 (arranged as 2 pairs with 2 enable inputs)
Enable Inputs 1C (enables latches 1&2), 2C (enables latches 3&4)
Outputs Q and Q̄ per latch (complementary)
Propagation Delay 14-30ns (D to Q)
Setup Time 20ns minimum
Hold Time 5ns minimum
Operating Temperature 0°C to +70°C
Package PDIP-16 (19.3 x 6.35mm)

Features

  • 4 D-type transparent latches
  • Two enable inputs (each controls 2 latches)
  • Complementary Q and Q̄ outputs
  • Transparent: Q follows D while enable is HIGH
  • Latched: Q holds when enable goes LOW
  • Diode-clamped inputs

Applications

  • Data holding registers
  • Address latching
  • I/O port buffering
  • Indicator drivers

The SN74LS75N from Texas Instruments is a 4-bit bistable transparent latch consisting of four D-type latches with two active-HIGH enable inputs. When the enable (C) is HIGH, the Q output follows the D input (transparent mode). When the enable goes LOW, the data present at D just before the transition is latched and held at Q. The four latches are arranged in two pairs: enable 1C controls latches 1 and 2; enable 2C controls latches 3 and 4. This dual-enable arrangement allows the 7475 to latch two 2-bit groups independently or one 4-bit group simultaneously (by tying 1C and 2C together). Each latch provides complementary Q and Q̄ outputs. The 7475 is the TTL equivalent of the CMOS CD4042 but without polarity control — it’s always transparent when the enable is HIGH. The 30ns propagation delay and 20ns setup time make it suitable for medium-speed digital systems. The N suffix denotes the PDIP-16 through-hole package.

Each latch in the SN74LS75N operates as a transparent D latch. When the enable input (C) is HIGH: Q follows D in real time; Q̄ follows D̄ (complement of D). When C transitions from HIGH to LOW: the data present at D at the moment of transition is captured and held at Q; Q̄ holds the complement. When C remains LOW: Q and Q̄ hold their latched values regardless of changes at D. The two enable inputs (1C and 2C) each control a pair of latches: 1C controls latches 1 and 2 (pins 2D,3D → 2Q,3Q); 2C controls latches 3 and 4 (pins 5D,6D → 5Q,6Q). For 4-bit simultaneous latching: tie 1C and 2C together; all four latches capture on the same enable transition. For independent 2-bit latching: separate 1C and 2C; each pair captures at different times. The 20ns setup time means D must be stable at least 20ns before C goes LOW; the 5ns hold time means D must remain stable for 5ns after C goes LOW.

Pin Name Type Description
1 1Q̄ Output Latch 1 complementary output
2 1Q Output Latch 1 true output
3 1D Input Latch 1 data input
4 2D Input Latch 2 data input
5 2Q Output Latch 2 true output
6 2Q̄ Output Latch 2 complementary output
7 GND Power Ground
8 3Q̄ Output Latch 3 complementary output
9 3Q Output Latch 3 true output
10 3D Input Latch 3 data input
11 4D Input Latch 4 data input
12 4Q Output Latch 4 true output
13 4Q̄ Output Latch 4 complementary output
14 2C Input Enable for latches 3 & 4 (active HIGH)
15 1C Input Enable for latches 1 & 2 (active HIGH)
16 VCC Power Supply (5V)
  • 4-Bit Data Latch: 4 data bits → 1D,2D,3D,4D; 1C and 2C tied together; enable pulse captures all 4 bits simultaneously; Q outputs held stable
  • 2+2 Independent Latching: 1C and 2C separate; 2-bit address latched by 1C; 2-bit data latched by 2C; independent timing
  • Address Latch (8051):

    Multiplexed AD0-AD3 → 1D-4D; ALE → 1C+2C; Q outputs = stable lower address bits

  • Indicator Driver: System status bits → D inputs; enable from control logic; Q̄ drives active-LOW LED indicators; Q drives active-HIGH
Model Manufacturer Key Difference Package Supply
74LS75N TI/Nexperia Original TTL version with 5V-only supply, typical propagation delay 10-15ns DIP-16 5V TTL
74LS75D TI/Nexperia Surface-mount SOIC version of LS with identical logic function SOIC-16 5V TTL
74HC75D TI/Nexperia CMOS version with wide 2-6V supply range, lower power consumption and higher noise immunity SOIC-16 2-6V CMOS
74HC75N TI/Nexperia Through-hole DIP version of HC family for prototyping and repair DIP-16 2-6V CMOS
74HCT75D TI/Nexperia CMOS with TTL-compatible input levels, ideal for mixing with LS devices at 5V SOIC-16 4.5-5.5V TTL-in
74HCT75N TI/Nexperia Through-hole DIP version of HCT family for prototyping and repair DIP-16 4.5-5.5V TTL-in

The 7475 is a 4-Bit Bistable Latch. Family variants span from the original LS TTL (5V only) to modern LVC/AUP (down to 0.8V). HC and HCT versions offer 2-6V CMOS operation with HCT providing TTL-compatible input thresholds for mixed 5V systems. CD4000-series equivalents offer the widest 3-18V supply range at the cost of lower switching speed. DIP packages (N suffix) are through-hole; SOIC (D suffix) and TSSOP are surface-mount.

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