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SN74LS373N

Octal transparent D-latch, 3-state out, single LE/OE, LS TTL, PDIP-20

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Manufacturer Part：

SN74LS373N

Package：

PDIP-20 (24.33 x 6.35 x 5.08mm, 2.54mm pitch, through-hole)

Brand：

Product Categories：

Integrated Circuits ICs, Interface ICs

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Description

Product Overview

The SN74LS373N is an octal transparent D-type latch with 3-state outputs from Texas Instruments, featuring separate output enable and latch enable controls in a 20-pin PDIP package.

Key Specifications

Number of Bits	8 (octal)
Logic Family	LS (Low-power Schottky)
Function	Transparent D-type latch
Supply Voltage	4.75V to 5.25V (5V nominal)
Propagation Delay (D to Q)	18ns typical
Latch Enable to Output	27ns typical
Output Type	3-state (high-impedance when disabled)
Output Enable (OE)	Active-low (single pin controls all 8 outputs)
Output Drive (IOL/IOH)	24mA / -2.6mA
Operating Temperature	0°C to +70°C
Package	PDIP-20 (24.33 x 6.35mm)

Features

8-bit transparent latch with 3-state outputs
Single latch enable (LE) controls all 8 latches
Single output enable (OE) controls all 8 outputs
When LE is HIGH, outputs follow inputs (transparent)
When LE goes LOW, data is latched and held
3-state outputs for bus-oriented applications
Direct replacement for 74LS373 from any manufacturer

Applications

Microprocessor address latch
Data register and hold register
Bus buffer and isolation
I/O port output register
Demultiplexed bus systems

Product Introduction:SN74LS373N Product Introduction

The SN74LS373N from Texas Instruments is an 8-bit transparent D-type latch with 3-state outputs, designed for bus-oriented applications in microprocessor and digital systems. When the Latch Enable (LE) input is HIGH, the latch is transparent—each output (Q) follows its corresponding data input (D). When LE transitions LOW, the data present at the inputs is latched and held at the outputs, regardless of subsequent input changes. The Output Enable (OE) input, when LOW, enables the 3-state output drivers; when OE is HIGH, all outputs enter the high-impedance state, effectively disconnecting the latch from the bus. This allows multiple SN74LS373 devices to share a common data bus. The device is commonly used in 8051 and similar microprocessor systems to demultiplex the address/data bus by latching the address on the falling edge of ALE. The N suffix denotes the PDIP-20 through-hole package.

Working Principle:SN74LS373N Working Principle

The SN74LS373N contains eight identical D-type transparent latches with common control inputs. Each latch has a data input (D) and a 3-state output (Q). When LE is HIGH, the latch is transparent: Q follows D with an 18ns propagation delay. This means the latch acts as a wire—data passes through unimpeded. When LE transitions from HIGH to LOW, the current D value is captured and held on Q. Subsequent changes on D are ignored until LE goes HIGH again. The OE control is independent of LE. When OE is LOW, the 3-state output buffers are active and Q drives the bus. When OE is HIGH, the output buffers enter the high-impedance state (both pull-up and pull-up transistors OFF), regardless of the latched data. This allows multiple 373 devices to share the same bus—only one should have OE LOW at a time. The typical application in 8051 systems: the multiplexed AD0-AD7 bus connects to the D inputs; the ALE signal connects to LE. During the address phase, ALE is HIGH and the address flows through to Q. When ALE falls, the address is latched. The bus then switches to data, but the latched address remains on Q for the duration of the bus cycle.

Pin Description:SN74LS373N Pin Definition and Functions

Pin	Name	Type	Description
1	OE	Input	Output enable (active low, 3-state control)
2	1Q	Output	Latch 1 output (3-state)
3	1D	Input	Latch 1 data input
4	2D	Input	Latch 2 data input
5	2Q	Output	Latch 2 output (3-state)
6	3Q	Output	Latch 3 output (3-state)
7	3D	Input	Latch 3 data input
8	4D	Input	Latch 4 data input
9	4Q	Output	Latch 4 output (3-state)
10	GND	Power	Ground
11	LE	Input	Latch enable (HIGH=transparent, LOW=latched)
12	5Q	Output	Latch 5 output (3-state)
13	5D	Input	Latch 5 data input
14	6D	Input	Latch 6 data input
15	6Q	Output	Latch 6 output (3-state)
16	7Q	Output	Latch 7 output (3-state)
17	7D	Input	Latch 7 data input
18	8D	Input	Latch 8 data input
19	8Q	Output	Latch 8 output (3-state)
20	VCC	Power	Supply (4.75V to 5.25V)

Application Scenarios:In which products and applications isSN74LS373N used

Mux Bus Demux: 8051 ALE signal latches lower address byte from multiplexed AD0-AD7 bus
Output Register: Write data to latch, disable LE; data holds on outputs until next write
Bus Isolation: OE=HIGH disconnects latch from shared bus; OE=LOW when this device drives the bus
Input Port: External signals pass through transparent latch when LE=HIGH; latch on LE=LOW to freeze during read
Pipeline Stage: LE strobes at each clock phase to create an 8-bit pipeline register

Alternative Models:What chips are recommended as replacements for SN74LS373N

Model	Manufacturer	Key Difference	Package	Supply
74LS373N	TI/Nexperia	Original TTL version with 5V-only supply, typical propagation delay 10-15ns	DIP-20	5V TTL
74LS373D	TI/Nexperia	Surface-mount SOIC version of LS with identical logic function	SOIC-20	5V TTL
74HC373D	TI/Nexperia	CMOS version with wide 2-6V supply range, lower power consumption and higher noise immunity	SOIC-20	2-6V CMOS
74HC373N	TI/Nexperia	Through-hole DIP version of HC family for prototyping and repair	DIP-20	2-6V CMOS
74HCT373D	TI/Nexperia	CMOS with TTL-compatible input levels, ideal for mixing with LS devices at 5V	SOIC-20	4.5-5.5V TTL-in
74HCT373N	TI/Nexperia	Through-hole DIP version of HCT family for prototyping and repair	DIP-20	4.5-5.5V TTL-in
74LVC373D	TI/Nexperia	Low-voltage CMOS for 1.65-3.6V modern logic with 24mA output drive and bus-hold inputs	SOIC-20	1.65-3.6V CMOS
74LVC373N	TI/Nexperia	Through-hole DIP version of LVC family for prototyping and repair	DIP-20	1.65-3.6V CMOS

The 74373 is a Octal Transparent Latch with 3-State Output. Family variants span from the original LS TTL (5V only) to modern LVC/AUP (down to 0.8V). HC and HCT versions offer 2-6V CMOS operation with HCT providing TTL-compatible input thresholds for mixed 5V systems. CD4000-series equivalents offer the widest 3-18V supply range at the cost of lower switching speed. DIP packages (N suffix) are through-hole; SOIC (D suffix) and TSSOP are surface-mount.