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SN74LS32N

Quad 2-input OR gate, LS TTL, 14ns, PDIP-14

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Manufacturer Part：

SN74LS32N

Package：

PDIP-14 (19.3 x 6.35 x 4.57mm, 2.54mm pitch, through-hole)

Brand：

Product Categories：

Integrated Circuits ICs, Interface ICs

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Description

Product Overview

The SN74LS32N is a quad 2-input OR gate from Texas Instruments with LS TTL technology, 14ns propagation delay, and industry-standard pinout in a 14-pin PDIP package.

Key Specifications

Number of Gates	4 (quad 2-input OR)
Logic Family	LS (Low-power Schottky)
Supply Voltage	4.75V to 5.25V (5V nominal)
Propagation Delay	14ns typical @ 5V
Output Drive (IOL/IOH)	8mA / -0.4mA
Operating Temperature	0°C to +70°C
Package	PDIP-14 (19.3 x 6.35mm)

Features

Four independent 2-input OR gates
LS TTL technology
14ns typical propagation delay
Industry-standard 7432 pinout
Input clamp diodes for undershoot protection

Applications

Logic OR function implementation
Interrupt signal combination
Alarm and fault aggregation
Address decoding logic
General-purpose logic gating

Product Introduction:SN74LS32N Product Introduction

The SN74LS32N from Texas Instruments contains four independent 2-input OR gates in a 14-pin PDIP through-hole package. Each gate performs the Boolean function Y = A OR B; the output is HIGH when either or both inputs are HIGH. The LS (Low-power Schottky) technology provides 14ns typical propagation delay with moderate power consumption. The device is one of the fundamental 7400-series logic ICs, useful for combining multiple active-HIGH signals into a single output. The N suffix denotes the PDIP-14 through-hole package.

Working Principle:SN74LS32N Working Principle

Each of the four OR gates in the SN74LS32N performs the Boolean function Y = A + B (inclusive OR). The output is LOW only when both inputs A and B are LOW; for all other input combinations (01, 10, 11), the output is HIGH. The LS TTL implementation uses diode-transistor logic for the input stage and a totem-pole output stage. The 14ns propagation delay means the output transitions approximately 14ns after the input changes. OR gates are commonly used to combine multiple interrupt request lines into a single interrupt input, where any source can trigger the interrupt. An OR gate can also be constructed from NAND gates (DeMorgan’s theorem: A+B = NOT(NOT(A) · NOT(B))), but the 7432 provides this function directly with fewer gates and lower delay.

Pin Description:SN74LS32N Pin Definition and Functions

Pin	Name	Type	Description
1	1A	Input	Gate 1 input A
2	1B	Input	Gate 1 input B
3	1Y	Output	Gate 1 output (OR)
4	2A	Input	Gate 2 input A
5	2B	Input	Gate 2 input B
6	2Y	Output	Gate 2 output (OR)
7	GND	Power	Ground
8	3Y	Output	Gate 3 output (OR)
9	3A	Input	Gate 3 input A
10	3B	Input	Gate 3 input B
11	4Y	Output	Gate 4 output (OR)
12	4A	Input	Gate 4 input A
13	4B	Input	Gate 4 input B
14	VCC	Power	Supply (4.75V to 5.25V)

Application Scenarios:In which products and applications isSN74LS32N used

Interrupt OR: Combine 2 active-HIGH interrupt lines into single MCU interrupt pin; any source triggers interrupt
Alarm Aggregation: Multiple fault signals ORed into single alarm; Y=HIGH when any fault is active
Address Decode: OR combines chip select from multiple address ranges into single peripheral enable
Enable Logic: Either of two enable signals activates the output; A OR B = enable
Signal Merge: Combine two clock or strobe signals where either one activates the next stage

Alternative Models:What chips are recommended as replacements for SN74LS32N

Model	Manufacturer	Key Difference	Package	Supply
74LS32N	TI/Nexperia	Original TTL version with 5V-only supply, typical propagation delay 10-15ns	DIP-14	5V TTL
74LS32D	TI/Nexperia	Surface-mount SOIC version of LS with identical logic function	SOIC-14	5V TTL
74HC32D	TI/Nexperia	CMOS version with wide 2-6V supply range, lower power consumption and higher noise immunity	SOIC-14	2-6V CMOS
74HC32N	TI/Nexperia	Through-hole DIP version of HC family for prototyping and repair	DIP-14	2-6V CMOS
74HCT32D	TI/Nexperia	CMOS with TTL-compatible input levels, ideal for mixing with LS devices at 5V	SOIC-14	4.5-5.5V TTL-in
74HCT32N	TI/Nexperia	Through-hole DIP version of HCT family for prototyping and repair	DIP-14	4.5-5.5V TTL-in
74AC32D	TI/Nexperia	Advanced CMOS with 2-6V supply and higher output drive current (24mA vs 6mA for HC)	SOIC-14	2-6V CMOS
74AC32N	TI/Nexperia	Through-hole DIP version of AC family for prototyping and repair	DIP-14	2-6V CMOS
74LVC32D	TI/Nexperia	Low-voltage CMOS for 1.65-3.6V modern logic with 24mA output drive and bus-hold inputs	SOIC-14	1.65-3.6V CMOS
74LVC32N	TI/Nexperia	Through-hole DIP version of LVC family for prototyping and repair	DIP-14	1.65-3.6V CMOS

The 7432 is a Quad 2-Input OR Gate. Family variants span from the original LS TTL (5V only) to modern LVC/AUP (down to 0.8V). HC and HCT versions offer 2-6V CMOS operation with HCT providing TTL-compatible input thresholds for mixed 5V systems. CD4000-series equivalents offer the widest 3-18V supply range at the cost of lower switching speed. DIP packages (N suffix) are through-hole; SOIC (D suffix) and TSSOP are surface-mount.