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SN74LS283N

4-bit binary full adder, carry lookahead, C0/C4 cascade, PDIP-16

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Manufacturer Part：

SN74LS283N

Package：

PDIP-16 (19.3 x 6.35 x 4.57mm, 2.54mm pitch, through-hole)

Brand：

Product Categories：

Integrated Circuits ICs, Interface ICs

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Description

Product Overview

The SN74LS283N from Texas Instruments is a 4-bit binary full adder with fast carry lookahead, performing addition of two 4-bit binary numbers plus a carry-in, producing a 4-bit sum and carry-out in a 16-pin PDIP package.

Key Specifications

Function	4-bit binary full adder with carry lookahead
Logic Family	LS (Low-power Schottky)
Supply Voltage	4.75V to 5.25V (5V nominal)
Inputs	Two 4-bit words (A1-A4, B1-B4) + Carry-In (C0)
Outputs	4-bit sum (Σ1-Σ4) + Carry-Out (C4)
Addition Time (C0 to C4)	10ns typical (carry propagation)
Addition Time (A/B to Σ)	25ns typical
Operating Temperature	0°C to +70°C
Package	PDIP-16 (19.3 x 6.35mm)

Features

4-bit binary addition with carry lookahead
Two independent 4-bit word inputs
Carry-in and carry-out for cascading
Fast carry propagation: 10ns typical
Full lookahead for minimum addition time

Applications

Arithmetic logic unit (ALU) implementation
Address calculation and incrementing
Multi-bit addition and subtraction
Digital signal processing arithmetic
Counter and accumulator circuits

Product Introduction:SN74LS283N Product Introduction

The SN74LS283N from Texas Instruments is a 4-bit binary full adder that adds two 4-bit binary numbers (A1-A4 and B1-B4) and a carry-in (C0) to produce a 4-bit sum (Σ1-Σ4) and a carry-out (C4). The carry-lookahead architecture generates the carry-out internally in only 10ns, much faster than a ripple-carry adder where the carry must propagate through all four stages sequentially. This makes the 74LS283 suitable for building wider adders by cascading multiple devices: two 74LS283s create an 8-bit adder by connecting the C4 of the lower-order adder to the C0 of the higher-order adder, with a total carry propagation of only 20ns (10ns per stage). For subtraction, the B input is complemented (using inverters or XOR gates) and C0 is set HIGH, implementing two’s complement subtraction. The N suffix denotes the PDIP-16 through-hole package.

Working Principle:SN74LS283N Working Principle

The SN74LS283N performs binary addition using carry-lookahead logic. The sum bits are computed as Σi = Ai XOR Bi XOR Ci, and the carry bits as Ci+1 = (Ai AND Bi) OR (Ci AND (Ai XOR Bi)). In a simple ripple-carry adder, each carry bit must be computed sequentially, creating a propagation delay proportional to the number of bits. The 74LS283 avoids this by computing the carry-lookahead functions in parallel: it generates generate (Gi = Ai AND Bi) and propagate (Pi = Ai XOR Bi) signals for all four bits, then computes C4 = G4 + P4·G3 + P4·P3·G2 + P4·P3·P2·G1 + P4·P3·P2·P1·C0 using only two levels of logic. This reduces the carry propagation from 4 gate delays to just 2. The sum bits are then computed using the pre-computed carries. For multi-bit addition, the C4 output connects to the C0 input of the next 74LS283. For 16-bit addition, four devices are cascaded with a total carry propagation of 40ns (10ns × 4 stages).

Pin Description:SN74LS283N Pin Definition and Functions

Pin	Name	Type	Description
1	Σ4	Output	Sum bit 4 (MSB)
2	Σ3	Output	Sum bit 3
3	A3	Input	Input A bit 3
4	B3	Input	Input B bit 3
5	VCC	Power	Supply (4.75V to 5.25V)
6	Σ2	Output	Sum bit 2
7	B2	Input	Input B bit 2
8	A2	Input	Input A bit 2
9	Σ1	Output	Sum bit 1 (LSB)
10	A1	Input	Input A bit 1 (LSB)
11	B1	Input	Input B bit 1 (LSB)
12	GND	Power	Ground
13	C0	Input	Carry input (from lower-order adder)
14	A4	Input	Input A bit 4 (MSB)
15	B4	Input	Input B bit 4 (MSB)
16	C4	Output	Carry output (to higher-order adder)

Application Scenarios:In which products and applications isSN74LS283N used

8-Bit Adder: Two 74LS283s cascaded; lower C4 → upper C0; 8-bit A + 8-bit B → 8-bit sum + carry
Subtractor: B inputs through XOR gates (controlled by SUB signal); C0 = SUB; when SUB=1, result = A – B
Address Increment: B = 0001, C0 = 0; Σ = A + 1 (program counter increment)
ALU Core: 74LS283 for addition; XOR for subtraction; AND/OR for logic; multiplexers select operation
Accumulator: D inputs from Σ outputs; clock captures result; feedback to A for running sum

Alternative Models:What chips are recommended as replacements for SN74LS283N

Model	Manufacturer	Key Difference	Package	Supply
74LS283N	TI/Nexperia	Original TTL version with 5V-only supply, typical propagation delay 10-15ns	DIP-16	5V TTL
74LS283D	TI/Nexperia	Surface-mount SOIC version of LS with identical logic function	SOIC-16	5V TTL
74HC283D	TI/Nexperia	CMOS version with wide 2-6V supply range, lower power consumption and higher noise immunity	SOIC-16	2-6V CMOS
74HC283N	TI/Nexperia	Through-hole DIP version of HC family for prototyping and repair	DIP-16	2-6V CMOS
74HCT283D	TI/Nexperia	CMOS with TTL-compatible input levels, ideal for mixing with LS devices at 5V	SOIC-16	4.5-5.5V TTL-in
74HCT283N	TI/Nexperia	Through-hole DIP version of HCT family for prototyping and repair	DIP-16	4.5-5.5V TTL-in

The 74283 is a 4-Bit Binary Full Adder. Family variants span from the original LS TTL (5V only) to modern LVC/AUP (down to 0.8V). HC and HCT versions offer 2-6V CMOS operation with HCT providing TTL-compatible input thresholds for mixed 5V systems. CD4000-series equivalents offer the widest 3-18V supply range at the cost of lower switching speed. DIP packages (N suffix) are through-hole; SOIC (D suffix) and TSSOP are surface-mount.