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SN74LS20N

Dual 4-input NAND gate, LS TTL, PDIP-14

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Manufacturer Part：

SN74LS20N

Package：

PDIP-14 (19.3 x 6.35 x 4.57mm, 2.54mm pitch, through-hole)

Brand：

Product Categories：

Integrated Circuits ICs, Interface ICs

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Description

Product Overview

The SN74LS20N from Texas Instruments contains two independent 4-input NAND gates in a 14-pin PDIP package — essential for decoding and multi-condition gating where all four conditions must be met.

Key Specifications

Number of Gates	2 (dual 4-input NAND)
Logic Family	LS (Low-power Schottky)
Supply Voltage	4.75V to 5.25V
Propagation Delay	10-15ns typical
Output Drive	IOL = 8mA, IOH = -0.4mA
Operating Temperature	0°C to +70°C
Package	PDIP-14 (19.3 x 6.35mm)

Features

Dual 4-input NAND gates
Output LOW only when ALL four inputs are HIGH
Active-LOW output enables multi-condition decoding
10-15ns propagation delay

Applications

Address decoding (4 conditions → 1 chip select)
Multi-condition gating
Control logic
General TTL logic

Product Introduction:SN74LS20N Product Introduction

The SN74LS20N from Texas Instruments contains two independent 4-input NAND gates. Each gate implements Y = NOT(A AND B AND C AND D); the output goes LOW only when all four inputs are HIGH. This is the 4-input extension of the 2-input NAND (7400) and is critical for address decoding and multi-condition logic. In address decoding, the 4-input NAND can decode a specific 4-bit address pattern: connect the 4 address lines (or their complements) so that the NAND output goes LOW only for the target address. For example, to decode address 1011: connect A3 (direct), A2 (inverted), A1 (direct), A0 (direct) to the NAND inputs; the output goes LOW only when A3=1, A2=0, A1=1, A0=1. The 4-input NAND provides 16 possible input combinations; only one produces a LOW output. The N suffix denotes the PDIP-14 through-hole package.

Working Principle:SN74LS20N Working Principle

Each 4-input NAND gate in the SN74LS20N performs Y = (A·B·C·D)’. The output is LOW only when all four inputs A, B, C, and D are simultaneously HIGH. For any other combination (at least one input LOW), the output is HIGH. The 4-input NAND is essentially an AND function followed by inversion, but implemented as a single gate for lower delay. By DeMorgan’s theorem: Y = A’ + B’ + C’ + D’ (OR of complements). This means the NAND output is HIGH if ANY input is LOW — making it useful as an ‘any-inactive’ detector. For address decoding: connect address lines (direct or inverted) so that the target address presents all HIGH inputs; the NAND output goes LOW, selecting the target device. For multi-condition gating: all four conditions must be active (HIGH) for the output to go LOW (active); any inactive condition forces the output HIGH. Unused inputs on a 4-input NAND should be tied HIGH (VCC) to not affect the logic; tying them LOW would force the output permanently HIGH.

Pin Description:SN74LS20N Pin Definition and Functions

Pin	Name	Type	Description
1	1A	Input	Gate 1 input A
2	1B	Input	Gate 1 input B
3	NC	—	No connection
4	1C	Input	Gate 1 input C
5	1D	Input	Gate 1 input D
6	1Y	Output	Gate 1 output
7	GND	Power	Ground
8	2Y	Output	Gate 2 output
9	2A	Input	Gate 2 input A
10	2B	Input	Gate 2 input B
11	NC	—	No connection
12	2C	Input	Gate 2 input C
13	2D	Input	Gate 2 input D
14	VCC	Power	Supply (5V)

SN74LS20N uses the PDIP-14 package with standard 74LS TTL pinout: VCC at Pin 14, GND at Pin 7. Each NAND gate has four inputs and one open-collector output — Gate 1: Pins 1-4 (inputs), Pin 6 (output); Gate 2: Pins 9-12 (inputs), Pin 8 (output). Pins 5 and 13 are not connected. The LS technology provides typical propagation delay of 15ns. The open-collector outputs allow wired-AND connections and level shifting to higher voltages. For push-pull active pull-up outputs, use SN74HC20N or SN74HCT20N which maintain the same pinout. The 5400 military-grade variant offers -55°C to +125°C operation.

Application Scenarios:In which products and applications isSN74LS20N used

4-Bit Address Decode: 4 address lines (with inverters as needed) → A,B,C,D; Y goes LOW only for target address; Y → chip select (active-LOW)
Multi-Condition Enable: 4 enable conditions → A,B,C,D; Y = LOW only when ALL enables are active; any condition missing = Y HIGH
2-to-4 Line Decoder: 2 address lines and their complements → two NAND gates; Y1 decodes address 00, Y2 decodes address 11; partial decoding
Combined with 7410: 7420 (4-input) + 7410 (3-input) NAND gates create complex decode logic for multi-bit addresses

Alternative Models:What chips are recommended as replacements for SN74LS20N

Model	Manufacturer	Key Difference	Package	Supply
74LS20N	TI/Nexperia	Original TTL version with 5V-only supply, typical propagation delay 10-15ns	DIP-14	5V TTL
74LS20D	TI/Nexperia	Surface-mount SOIC version of LS with identical logic function	SOIC-14	5V TTL
74HC20D	TI/Nexperia	CMOS version with wide 2-6V supply range, lower power consumption and higher noise immunity	SOIC-14	2-6V CMOS
74HC20N	TI/Nexperia	Through-hole DIP version of HC family for prototyping and repair	DIP-14	2-6V CMOS
74HCT20D	TI/Nexperia	CMOS with TTL-compatible input levels, ideal for mixing with LS devices at 5V	SOIC-14	4.5-5.5V TTL-in
74HCT20N	TI/Nexperia	Through-hole DIP version of HCT family for prototyping and repair	DIP-14	4.5-5.5V TTL-in
74AC20D	TI/Nexperia	Advanced CMOS with 2-6V supply and higher output drive current (24mA vs 6mA for HC)	SOIC-14	2-6V CMOS
74AC20N	TI/Nexperia	Through-hole DIP version of AC family for prototyping and repair	DIP-14	2-6V CMOS
74LVC20D	TI/Nexperia	Low-voltage CMOS for 1.65-3.6V modern logic with 24mA output drive and bus-hold inputs	SOIC-14	1.65-3.6V CMOS
74LVC20N	TI/Nexperia	Through-hole DIP version of LVC family for prototyping and repair	DIP-14	1.65-3.6V CMOS

The 7420 is a Dual 4-Input NAND Gate. Family variants span from the original LS TTL (5V only) to modern LVC/AUP (down to 0.8V). HC and HCT versions offer 2-6V CMOS operation with HCT providing TTL-compatible input thresholds for mixed 5V systems. CD4000-series equivalents offer the widest 3-18V supply range at the cost of lower switching speed. DIP packages (N suffix) are through-hole; SOIC (D suffix) and TSSOP are surface-mount.