Home > Integrated Circuits ICs > SN74LS126N

SN74LS126N

Quad 3-state bus buffer, active-HIGH enable, LS TTL, PDIP-14

5000

Effective Inventory

Go to Inquiry

Image for reference only

Manufacturer Part：

SN74LS126N

Package：

PDIP-14 (19.3 x 6.35 x 4.57mm, 2.54mm pitch, through-hole)

Brand：

Product Categories：

Integrated Circuits ICs, Interface ICs

Other recommendations you may be interested in.

SII9396SCNUC-BAR

IS43TR16256BL-125KBLI

Description

Product Overview

The SN74LS126N from Texas Instruments contains four independent bus buffer gates with 3-state outputs and active-HIGH output enable, designed for bus-oriented systems in a 14-pin PDIP package.

Key Specifications

Number of Gates	4 (quad bus buffer, 3-state)
Logic Family	LS (Low-power Schottky)
Supply Voltage	4.75V to 5.25V
Output Enable	Active-HIGH (HIGH=enabled, LOW=high-Z)
Propagation Delay	9ns typical
Output Drive (IOL/IOH)	24mA / -2.6mA (bus driver)
3-State Output Current	20µA max (high-Z leakage)
Operating Temperature	0°C to +70°C
Package	PDIP-14 (19.3 x 6.35mm)

Features

Four non-inverting bus buffers with 3-state outputs
Active-HIGH output enable
24mA output sink current — bus driver capability
High-Z state when disabled (only 20µA leakage)
Complement to 74125 (active-LOW enable)

Applications

Microprocessor bus interface
Multi-device shared bus
I/O port expansion
Data routing and isolation

Product Introduction:SN74LS126N Product Introduction

The SN74LS126N from Texas Instruments contains four independent non-inverting buffer gates with 3-state (high-impedance) outputs controlled by active-HIGH enable pins. When the output enable (OE) is HIGH, the buffer passes data from input to output with no inversion: Y = A. When OE is LOW, the output enters a high-impedance (high-Z) state, effectively disconnecting from the bus — only 20µA of leakage current flows. This 3-state capability is essential for bus-oriented systems where multiple devices share a common data bus: only one device drives the bus at a time (OE=HIGH), while all others are in high-Z (OE=LOW). The 24mA sink capability makes the 74126 suitable for driving heavily loaded bus lines. The active-HIGH enable is the complement of the 74125 (active-LOW enable). The N suffix denotes the PDIP-14 through-hole package.

Working Principle:SN74LS126N Working Principle

Each buffer in the SN74LS126N has two inputs: a data input (A) and an output enable (OE). When OE=HIGH, the output Y follows input A (non-inverting): Y = A. When OE=LOW, the output transistors are both turned off, placing the output in a high-impedance state where it neither sources nor sinks significant current (<20µA). In a bus system, the 74126 serves as a 'gate' that connects or disconnects a device from the shared bus. A decoder (like 74LS138) generates the enable signals, ensuring only one 74126 is active at any time. If two buffers drive the bus simultaneously with conflicting data, a bus contention occurs — large current flows between the conflicting outputs, potentially damaging the devices. The 74126's 24mA sink capability means it can drive long PCB traces or backplane bus lines with significant capacitive loading. The 9ns propagation delay is fast enough for microprocessor bus cycles.

Pin Description:SN74LS126N Pin Definition and Functions

Pin	Name	Type	Description
1	1OE	Input	Gate 1 output enable (active HIGH)
2	1A	Input	Gate 1 data input
3	1Y	Output	Gate 1 output (3-state)
4	2OE	Input	Gate 2 output enable
5	2A	Input	Gate 2 data input
6	2Y	Output	Gate 2 output (3-state)
7	GND	Power	Ground
8	3Y	Output	Gate 3 output (3-state)
9	3A	Input	Gate 3 data input
10	3OE	Input	Gate 3 output enable
11	4Y	Output	Gate 4 output (3-state)
12	4A	Input	Gate 4 data input
13	4OE	Input	Gate 4 output enable
14	VCC	Power	Supply (5V)

Application Scenarios:In which products and applications isSN74LS126N used

4-Bit Bus Interface: 4 data bits from peripheral → 74126 inputs; decoder generates OE for one device at a time; shared bus → CPU
Output Port: CPU data bus → 74126 inputs; OE tied to I/O write signal; 74126 outputs drive external devices when CPU writes
Bus Isolation: When system not accessing a module, OE=LOW → module’s 74126 outputs float; no bus loading
With 74LS125: Mix 74126 (active-HIGH OE) and 74125 (active-LOW OE) for different enable polarities in same bus system

Alternative Models:What chips are recommended as replacements for SN74LS126N

Model	Manufacturer	Key Difference	Package	Supply
74LS126N	TI/Nexperia	Original TTL version with 5V-only supply, typical propagation delay 10-15ns	DIP-14	5V TTL
74LS126D	TI/Nexperia	Surface-mount SOIC version of LS with identical logic function	SOIC-14	5V TTL
74HC126D	TI/Nexperia	CMOS version with wide 2-6V supply range, lower power consumption and higher noise immunity	SOIC-14	2-6V CMOS
74HC126N	TI/Nexperia	Through-hole DIP version of HC family for prototyping and repair	DIP-14	2-6V CMOS
74HCT126D	TI/Nexperia	CMOS with TTL-compatible input levels, ideal for mixing with LS devices at 5V	SOIC-14	4.5-5.5V TTL-in
74HCT126N	TI/Nexperia	Through-hole DIP version of HCT family for prototyping and repair	DIP-14	4.5-5.5V TTL-in
74LVC126D	TI/Nexperia	Low-voltage CMOS for 1.65-3.6V modern logic with 24mA output drive and bus-hold inputs	SOIC-14	1.65-3.6V CMOS
74LVC126N	TI/Nexperia	Through-hole DIP version of LVC family for prototyping and repair	DIP-14	1.65-3.6V CMOS

The 74126 is a Quad Bus Buffer with 3-State Output (Active-High Enable). Family variants span from the original LS TTL (5V only) to modern LVC/AUP (down to 0.8V). HC and HCT versions offer 2-6V CMOS operation with HCT providing TTL-compatible input thresholds for mixed 5V systems. CD4000-series equivalents offer the widest 3-18V supply range at the cost of lower switching speed. DIP packages (N suffix) are through-hole; SOIC (D suffix) and TSSOP are surface-mount.