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SN74LS109N

Dual J-K flip-flop, positive-edge, preset/clear, LS TTL, PDIP-16

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Manufacturer Part：

SN74LS109N

Package：

PDIP-16 (19.3 x 6.35 x 4.57mm, 2.54mm pitch, through-hole)

Brand：

Product Categories：

Integrated Circuits ICs, Interface ICs

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Description

Product Overview

The SN74LS109N from Texas Instruments contains two independent J-K positive-edge-triggered flip-flops with complementary outputs, preset and clear — the positive-edge version of the 7476 in a 16-pin PDIP package.

Key Specifications

Number of Flip-Flops	2 (dual, independent)
Logic Family	LS (Low-power Schottky)
Trigger Type	Positive-edge (rising edge of CLK)
Supply Voltage	4.75V to 5.25V
Max Clock Frequency	25MHz typical
Preset (PRE)	Active-LOW (asynchronous, sets Q=1)
Clear (CLR)	Active-LOW (asynchronous, sets Q=0)
Propagation Delay	16ns typical (CLK to Q)
Operating Temperature	0°C to +70°C
Package	PDIP-16 (19.3 x 6.35mm)

Features

Dual J-K positive-edge-triggered flip-flops
Active-LOW preset and clear (asynchronous)
Complementary outputs (Q and NOT-Q)
Toggle mode: J=1,K=1
Same pinout as SN74LS73N but with preset

Applications

Synchronous counters
Toggle flip-flops / frequency dividers
Control logic
Data registers

Product Introduction:SN74LS109N Product Introduction

The SN74LS109N from Texas Instruments contains two independent J-K positive-edge-triggered flip-flops with direct preset (PRE, active-LOW) and clear (CLR, active-LOW). It combines the J-K functionality of the 7476 with the positive-edge triggering of the 7474 D flip-flop. On each rising clock edge, the Q output is updated based on the J and K inputs: J=0,K=0 → hold; J=1,K=0 → set (Q=1); J=0,K=1 → reset (Q=0); J=1,K=1 → toggle. The positive-edge triggering makes the 74109 compatible with synchronous counter designs where all flip-flops share a common clock and update simultaneously — unlike the 7476’s negative-edge triggering which can cause ripple delays in synchronous systems. The active-LOW preset and clear override the clocked operation. The 74109 is the preferred J-K flip-flop for synchronous counter design because the positive-edge triggering aligns with the standard clock convention. The N suffix denotes the PDIP-16 through-hole package.

Working Principle:SN74LS109N Working Principle

Each J-K flip-flop in the SN74LS109N captures the J and K input states on the rising edge of CLK and updates Q accordingly. Truth table (on rising CLK edge): J=0,K=0 → Q holds; J=1,K=0 → Q=1 (set); J=0,K=1 → Q=0 (reset); J=1,K=1 → Q toggles. The asynchronous inputs override: PRE=LOW forces Q=1; CLR=LOW forces Q=0. For normal operation, PRE and CLR must both be HIGH. The positive-edge triggering means all flip-flops in a synchronous system update at the same time when they share a common clock — critical for synchronous counter design where ripple delays would cause incorrect operation. For a synchronous 2-bit counter: both 74109 flip-flops share the same CLK; FF1 J=K=1 (always toggle); FF2 J=K=Q1 (toggle only when Q1=1); both update simultaneously on each clock edge, counting 00→01→10→11→00. This avoids the ripple delay of cascaded negative-edge counters (like 7476).

Pin Description:SN74LS109N Pin Definition and Functions

Pin	Name	Type	Description
1	1CLR	Input	Flip-flop 1 clear (active LOW)
2	1J	Input	Flip-flop 1 J input
3	1K	Input	Flip-flop 1 K input (K̄ in some sources)
4	1CLK	Input	Flip-flop 1 clock (positive edge)
5	1PRE	Input	Flip-flop 1 preset (active LOW)
6	1Q	Output	Flip-flop 1 Q output
7	1NOT-Q	Output	Flip-flop 1 complementary output
8	GND	Power	Ground
9	2NOT-Q	Output	Flip-flop 2 complementary output
10	2Q	Output	Flip-flop 2 Q output
11	2PRE	Input	Flip-flop 2 preset (active LOW)
12	2CLK	Input	Flip-flop 2 clock (positive edge)
13	2K	Input	Flip-flop 2 K input
14	2J	Input	Flip-flop 2 J input
15	2CLR	Input	Flip-flop 2 clear (active LOW)
16	VCC	Power	Supply (5V)

Application Scenarios:In which products and applications isSN74LS109N used

Synchronous 2-Bit Counter: Shared CLK; FF1: J=K=1; FF2: J=K=Q1; both update simultaneously; counts 00→01→10→11→00
Toggle / ÷2: J=K=1 (tied HIGH); clock on CLK; Q toggles each rising edge
Controlled Toggle: J=enable, K=enable; enable=HIGH → toggle; enable=LOW → hold
D Flip-Flop Substitute: J=data, K=NOT-data (via inverter); Q = data on rising CLK edge

Alternative Models:What chips are recommended as replacements for SN74LS109N

Model	Manufacturer	Key Difference	Package	Supply
74LS109N	TI/Nexperia	Original TTL version with 5V-only supply, typical propagation delay 10-15ns	DIP-16	5V TTL
74LS109D	TI/Nexperia	Surface-mount SOIC version of LS with identical logic function	SOIC-16	5V TTL
74HC109D	TI/Nexperia	CMOS version with wide 2-6V supply range, lower power consumption and higher noise immunity	SOIC-16	2-6V CMOS
74HC109N	TI/Nexperia	Through-hole DIP version of HC family for prototyping and repair	DIP-16	2-6V CMOS
74HCT109D	TI/Nexperia	CMOS with TTL-compatible input levels, ideal for mixing with LS devices at 5V	SOIC-16	4.5-5.5V TTL-in
74HCT109N	TI/Nexperia	Through-hole DIP version of HCT family for prototyping and repair	DIP-16	4.5-5.5V TTL-in

The 74109 is a Dual J-K Positive-Edge-Triggered Flip-Flop. Family variants span from the original LS TTL (5V only) to modern LVC/AUP (down to 0.8V). HC and HCT versions offer 2-6V CMOS operation with HCT providing TTL-compatible input thresholds for mixed 5V systems. CD4000-series equivalents offer the widest 3-18V supply range at the cost of lower switching speed. DIP packages (N suffix) are through-hole; SOIC (D suffix) and TSSOP are surface-mount.