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SN74HC595N

8-bit shift register with latch, 3-state, daisy-chain, PDIP-16

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Manufacturer Part：

SN74HC595N

Package：

PDIP-16 (19.3 x 6.35 x 4.57mm, 2.54mm pitch, through-hole)

Brand：

Product Categories：

Integrated Circuits ICs, Interface ICs

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Description

Product Overview

The SN74HC595N from Texas Instruments is an 8-bit serial-in/parallel-out shift register with output latch and 3-state outputs, controllable via just 3 MCU pins, in a 16-pin PDIP package.

Key Specifications

Function	8-bit shift register with output latch
Logic Family	HC (High-speed CMOS)
Supply Voltage	2V to 6V
Shift Clock Frequency	52MHz typical @ 6V
Output Type	3-state (OE control)
Output Drive	±6mA @ 6V
Serial Data Input	SER (pin 14)
Shift Clock	SRCLK (pin 11, rising edge)
Latch Clock	RCLK (pin 12, rising edge)
Output Enable	OE (pin 13, active LOW)
Master Reset	SRCLR (pin 10, active LOW)
Cascade Output	Q7′ (pin 9, serial out for daisy-chain)
Operating Temperature	-40°C to +85°C
Package	PDIP-16 (19.3 x 6.35mm)

Features

8-bit serial-to-parallel conversion
Separate shift and latch clocks
3-state outputs for bus sharing
Daisy-chainable via Q7′ output
Asynchronous master reset (SRCLR)
Only 3 MCU pins needed for 8 outputs
Wide supply range: 2V to 6V

Applications

LED matrix column/row driver
7-segment display multiplexing
Expanding MCU output pins
SPI-controlled parallel output
Cascaded display chains

Product Introduction:SN74HC595N Product Introduction

The SN74HC595N from Texas Instruments is an 8-bit serial-in/parallel-out shift register with an output latch and 3-state outputs, allowing a microcontroller to control 8 (or more, via daisy-chaining) output lines using only 3 GPIO pins: SER (data), SRCLK (shift clock), and RCLK (latch clock). The shift register and output latch are separate: data shifts through the 8-bit register on each rising edge of SRCLK, but the outputs don’t change until a rising edge on RCLK transfers the shift register contents to the output latch. This prevents output glitches during shifting. The Q7′ output provides the serial data that overflows from the 8th stage, connecting to the SER input of the next 595 for daisy-chaining — with two 595s, 3 MCU pins control 16 outputs. The 3-state outputs (controlled by OE) allow multiple 595s to share an output bus. The master reset (SRCLR) clears the shift register asynchronously. The N suffix denotes the PDIP-16 through-hole package.

Working Principle:SN74HC595N Working Principle

The SN74HC595N has two 8-bit registers: a shift register and an output (storage) register. On each rising edge of SRCLK, the serial data at SER is shifted into the first stage of the shift register, and all existing data shifts one position toward the output. After 8 clock cycles, the first bit shifted in appears at the last stage (Q7′) ready for the next chip in a daisy chain. The shift register contents are NOT directly connected to the output pins. When a rising edge occurs on RCLK, the entire 8-bit shift register is copied to the output latch, and the 8 output pins (Q0-Q7) update simultaneously. This two-stage architecture prevents the outputs from flickering during the shifting process. The output enable (OE, active LOW) controls the 3-state output buffers: when OE is HIGH, all outputs are high-impedance; when LOW, the latched data drives the outputs. The master reset (SRCLR, active LOW) clears the shift register to all zeros without affecting the output latch. To send 8 bits: (1) Shift in all 8 bits via SER and SRCLK, (2) Pulse RCLK HIGH to latch, (3) Set OE LOW to enable outputs. For daisy-chaining: after shifting 16 bits through two chips (the first 8 bits end up in the second chip), pulse RCLK once to latch both chips simultaneously.

Pin Description:SN74HC595N Pin Definition and Functions

Pin	Name	Type	Description
1	Q1	Output	Parallel output bit 1
2	Q2	Output	Parallel output bit 2
3	Q3	Output	Parallel output bit 3
4	Q4	Output	Parallel output bit 4
5	Q5	Output	Parallel output bit 5
6	Q6	Output	Parallel output bit 6
7	Q7	Output	Parallel output bit 7
8	GND	Power	Ground
9	Q7′	Output	Serial output (for daisy-chain to next SER)
10	SRCLR	Input	Shift register clear (active LOW)
11	SRCLK	Input	Shift register clock (rising edge)
12	RCLK	Input	Storage register clock (rising edge, latch)
13	OE	Input	Output enable (active LOW; HIGH = 3-state)
14	SER	Input	Serial data input
15	Q0	Output	Parallel output bit 0
16	VCC	Power	Supply (2V to 6V)

Application Scenarios:In which products and applications isSN74HC595N used

8-LED Control: MCU SPI → SER+SRCLK; 8 bits shifted in; RCLK pulse latches; 8 LEDs on Q0-Q7; only 3 pins used
Daisy Chain (16+ outputs): Q7′ of first → SER of second; shift 16 bits; one RCLK pulse; 3 pins control 16+ outputs
7-Segment Display: 595 drives 7 segments + decimal point; multiplex with another 595 for digit select; 3 pins for 4+ digits
LED Matrix: Row 595 + Column 595; shift row and column data; 6 pins (3 per 595) control 8×8=64 LEDs
Relay Board: 8 relays on Q0-Q7; 3 pins from MCU; ULN2803 between 595 and relay coils for current

Alternative Models:What chips are recommended as replacements for SN74HC595N

Model	Manufacturer	Key Difference	Package	Supply
74HC595D	TI/Nexperia	CMOS version with wide 2-6V supply range, lower power consumption and higher noise immunity	SOIC-16	2-6V CMOS
74HC595N	TI/Nexperia	Through-hole DIP version of HC family for prototyping and repair	DIP-16	2-6V CMOS
74HCT595D	TI/Nexperia	CMOS with TTL-compatible input levels, ideal for mixing with LS devices at 5V	SOIC-16	4.5-5.5V TTL-in
74HCT595N	TI/Nexperia	Through-hole DIP version of HCT family for prototyping and repair	DIP-16	4.5-5.5V TTL-in
74LVC595D	TI/Nexperia	Low-voltage CMOS for 1.65-3.6V modern logic with 24mA output drive and bus-hold inputs	SOIC-16	1.65-3.6V CMOS
74LVC595N	TI/Nexperia	Through-hole DIP version of LVC family for prototyping and repair	DIP-16	1.65-3.6V CMOS
74AUP595D	TI/Nexperia	Ultra-low power CMOS with 0.8-3.6V supply for battery-powered and mobile applications	SOIC-16	0.8-3.6V CMOS
74AUP595N	TI/Nexperia	Through-hole DIP version of AUP family for prototyping and repair	DIP-16	0.8-3.6V CMOS

The 74595 is a 8-Bit Shift Register with Output Latches and 3-State Output. Family variants span from the original LS TTL (5V only) to modern LVC/AUP (down to 0.8V). HC and HCT versions offer 2-6V CMOS operation with HCT providing TTL-compatible input thresholds for mixed 5V systems. CD4000-series equivalents offer the widest 3-18V supply range at the cost of lower switching speed. DIP packages (N suffix) are through-hole; SOIC (D suffix) and TSSOP are surface-mount.