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SN74HC138DR

3-to-8 Decoder/Demux, 2-6V, active-low outputs, SOIC-16

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Manufacturer Part：

SN74HC138DR

Package：

SOIC-16 (9.9×3.9 mm, 1.27mm pitch)

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Description

Product Overview

The SN74HC138DR is a 3-line to 8-line decoder/demultiplexer from Texas Instruments. It accepts a 3-bit binary input and activates one of eight mutually exclusive outputs. With active-low outputs and multiple enable inputs, it is widely used for address decoding, data demultiplexing, and chip-select generation in digital systems. Packaged in SOIC-16.

Key Specifications

Logic Family 74HC (High-speed CMOS)
Function 3-to-8 Decoder/Demultiplexer
Supply Voltage Range 2.0V to 6.0V
Propagation Delay ~25 ns at 5V
Output Drive ±5.2 mA at 5V
Inputs 3 address (A, B, C) + 3 enable (G1, G2A, G2B)
Outputs 8 active-low (Y0-Y7)
Quiescent Current 40 µA max at 25°C
Operating Temperature -40°C to +85°C
Package SOIC-16 (3.9 mm width)

Features

  • 3-to-8 line decoding with active-low outputs
  • Three enable inputs (one active-high, two active-low) for easy cascading
  • Mutually exclusive output selection
  • Standard 74HC pinout compatible across manufacturers
  • Low quiescent power consumption
  • Input clamp diodes for overvoltage protection

Applications

  • Memory address decoding and chip-select generation
  • Data demultiplexing in digital communication
  • I/O port expansion with enable gating
  • Clock distribution and enable signal routing
  • Cascaded decoding for larger address spaces

The SN74HC138DR from Texas Instruments is a 3-line to 8-line decoder/demultiplexer in the 74HC logic family. It accepts a 3-bit binary address and activates one of eight active-low outputs. Three enable inputs (G1 active-high, G2A and G2B active-low) allow easy cascading for larger decoding applications. Operating from 2V to 6V with low quiescent current, it is ideal for address decoding and data routing in digital systems.

The SN74HC138DR decodes a 3-bit binary input (A, B, C) to activate one of eight outputs (Y0-Y7). The outputs are active-low, meaning the selected output goes LOW while all others remain HIGH. The device is enabled only when G1 is HIGH and both G2A and G2B are LOW. If any enable condition is not met, all outputs are forced HIGH (inactive). The internal logic consists of AND-OR gates that implement the demultiplexing function, with the enable inputs ANDed into each output gate to provide the global enable function.

Pin Name Type Function
1 A Input Address input LSB
2 B Input Address input middle bit
3 C Input Address input MSB
4 G2A Input Enable (active-low)
5 G2B Input Enable (active-low)
6 G1 Input Enable (active-high)
7 Y7 Output Decoded output 7 (active-low)
8 GND Power Ground
9 Y6 Output Decoded output 6 (active-low)
10 Y5 Output Decoded output 5 (active-low)
11 Y4 Output Decoded output 4 (active-low)
12 Y3 Output Decoded output 3 (active-low)
13 Y2 Output Decoded output 2 (active-low)
14 Y1 Output Decoded output 1 (active-low)
15 Y0 Output Decoded output 0 (active-low)
16 VCC Power Supply voltage (2-6V)
  • Memory address decoding for microprocessor systems
  • Chip-select generation for multiple peripheral ICs
  • Data demultiplexing in digital communication systems
  • I/O port expansion using enable gating logic
  • Cascaded decoding for 4-to-16 or larger address spaces
Manufacturer Part Number Package Notes
Nexperia 74HC138D SOIC-16 Direct equivalent from Nexperia
ON Semiconductor MC74HC138ADR2G SOIC-16 Direct equivalent from onsemi
Toshiba TC74HC138AP DIP-16 Through-hole equivalent
TI SN74HC138N DIP-16 Through-hole version
Nexperia 74HCT138D SOIC-16 TTL input level variant
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