NC7SZ11P6X

The NC7SZ11P6X is a single 3-input AND gate from onsemi’s TinyLogic UHS (Ultra High Speed) family, originally designed by Fairchild Semiconductor before its acquisition by onsemi. The device is fabricated with advanced CMOS technology to achieve high speed with high output drive while maintaining low static power dissipation across the 1.65-V to 5.5-V operating range.

The 3-input AND function computes Y = A AND B AND C. The output goes high only when all three inputs are high. This is useful for multi-condition enable circuits, address decoding, and fault detection where three independent conditions must all be satisfied before an action is taken.

The 2.7-ns typical propagation delay at 5 V (7.5-ns max with 50-pF load) makes the NC7SZ11 suitable for high-speed digital logic. The ±32-mA output drive at 5 V can directly drive LEDs, relay coils, and multiple TTL/CMOS inputs without a buffer.

The inputs tolerate voltages up to 7 V independently of VCC, enabling the device to accept 5-V signals even when operating at 1.8-V VCC. This is valuable for voltage translation — a 5-V input signal is correctly recognized as a logic high even when the gate is powered from 1.8 V, and the 1.8-V output is compatible with downstream 1.8-V logic.

When VCC is 0 V, the inputs and output are high-impedance, preventing backflow current in partially-powered systems. The 2-µA maximum quiescent current makes the device suitable for always-on logic.

The SC-70-6 (SOT-363) package occupies only 2.5 mm² of board area — one of the smallest logic gate packages available. This makes the NC7SZ11 ideal for adding glue logic in space-constrained designs where a full PLD or CPLD would be overkill.

The P6X suffix denotes SC-70-6 tape-and-reel packaging. Other package options include P5X (SOT-23-5) and M5X (MicroPak-5).

**CMOS AND Gate Logic:** The NC7SZ11 implements the Boolean AND function (Y = A · B · C) using complementary CMOS transistors. The input stage consists of three series-connected NMOS transistors and three parallel-connected PMOS transistors. When all three inputs are high, all three NMOS transistors conduct (creating a path from output to ground through the series chain), and all three PMOS transistors are off. When any input is low, the corresponding NMOS transistor turns off (breaking the series chain) and the corresponding PMOS transistor turns on (creating a path from VCC to output).

**Over-Voltage Tolerant Inputs:** The input structures use a special circuit that allows input voltages to exceed VCC up to 7 V. This is achieved by isolating the input protection diodes from the VCC rail and using a floating n-well structure. When an input exceeds VCC, the parasitic diode to VCC is reverse-biased, preventing current flow into VCC.

**Power-Off High-Impedance:** When VCC = 0 V, an internal circuit disables the output driver, placing the output in a high-impedance state. This prevents the device from sourcing or sinking current when unpowered, which is critical in hot-swap and multi-voltage systems.

**EMI Reduction:** The patented noise/EMI reduction circuitry slows the output edge rate slightly (controlled slew rate) to reduce high-frequency spectral content that causes electromagnetic interference, while maintaining acceptable propagation delay.