NC7SB3157P6X

The NC7SB3157 from onsemi’s TinyLogic family (originally Fairchild, also sold as FSA3157) is a single-pole/double-throw (SPDT) analog switch that functions as a 2:1 multiplexer or 1:2 demultiplexer. The NC7SB3157P6X is the SC-70-6 tape-and-reel version with 3000 units per reel.

The device routes the common port A to either B0 or B1 based on the select (S) pin logic level. When S is LOW, A connects to B0; when S is HIGH, A connects to B1. The break-before-make circuitry ensures both switches are never simultaneously on during a select transition, preventing momentary short circuits between B0 and B1.

The 3 Ohm typical on-resistance at 4.5 V (7 Ohm max) introduces minimal voltage drop and signal distortion. Rail-to-rail signal handling allows the switch to pass analog signals from 0 V to VCC without clipping. The 250 MHz -3 dB bandwidth supports high-speed digital and video signal routing.

The device operates from 1.65 V to 5.5 V, covering all common logic voltages (1.8 V, 2.5 V, 3.3 V, 5 V). The control input tolerates voltages up to 7 V independently of VCC, enabling 5 V control signals in 3.3 V systems without level translation.

Power-down high-impedance on all I/O pins prevents backflow current when VCC is 0 V, supporting hot-swap and partial-power applications. The off-state leakage current is only 0.05 uA typical (1 uA max), ensuring minimal signal coupling in the off state.

Note: The NC7SB3157P6X-F40 variant (with -F40 suffix) has been marked obsolete by DigiKey. The base NC7SB3157P6X may still be available from other distributors. The FSA3157P6X is the same device from the Fairchild product line and may be used as a cross-reference.

**CMOS Transmission Gate Switch:** Each switch path (A-B0, A-B1) uses a CMOS transmission gate (parallel NMOS + PMOS). The NMOS passes signals near VCC well, while the PMOS passes signals near GND well. Together, they provide rail-to-rail signal handling with relatively flat on-resistance across the full voltage range.

**Break-Before-Make:** During a select pin transition, the currently-on switch opens before the new switch closes. This prevents a momentary low-impedance path between B0 and B1 that could cause current spikes or signal glitches. The break-before-make delay is built into the internal control logic.

**Select Logic:** The S pin controls which switch is on. S = LOW: A-B0 connected, A-B1 open. S = HIGH: A-B1 connected, A-B0 open. The select pin has CMOS input thresholds (0.7 VCC for VIH, 0.3 VCC for VIL at 2.3-5.5 V) and tolerates voltages up to 7 V regardless of VCC.

**Over-Voltage Tolerance:** When VCC is 0 V, all I/O pins enter a high-impedance state, preventing any current path between ports or into the supply. This enables hot-swap and live-insertion applications where cards may be plugged into powered systems.