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LT1764AEFE#PBF

3A low-noise LDO, adjustable output, 40uVRms noise, 340mV dropout, programmable current limit in TSSOP-16E

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Manufacturer Part：

LT1764AEFE#PBF

Package：

TSSOP-16E (5.00 x 4.40 x 1.00 mm) with exposed pad

Brand：

Product Categories：

Integrated Circuits ICs, Low Dropout Regulators (LDO)

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Description

Product Overview

The LT1764AEFE#PBF from Analog Devices (Linear Technology) is a 3A low-noise LDO linear regulator in a TSSOP-16E package with exposed pad. The A suffix denotes the adjustable output version, featuring 40uVRms output noise, 340mV dropout at 3A, and 1mA quiescent current, suitable for high-current noise-sensitive power rails.

Key Specifications

Output Voltage	Adjustable (A version)
Output Current	3A
Input Voltage Range	2.7V ~ 20V
Dropout Voltage	340mV (Typical) @ 3A
Output Noise	40uVRms (Typical, 0.1Hz-100kHz)
Quiescent Current	1mA (Typical)
Shutdown Current	<1uA
Minimum Output Capacitor	10uF (Ceramic)
Package	TSSOP-16E (5.00 x 4.40mm, exposed pad)
Operating Temperature	-40°C ~ +125°C

Features

High 3A output current with low 340mV dropout
Low 40uVRms output noise for high-current analog supplies
Externally programmable current limit
Shutdown mode draws less than 1uA
Stable with 10uF ceramic output capacitor
Thermal shutdown and current limit protection
Adjustable output via external resistor divider
Exposed pad for superior thermal performance

Applications

FPGA and DSP core voltage regulation
High-speed ADC/DAC power supplies
RF power amplifier bias supplies
Post-regulation for switching supplies
Battery charger termination circuits

Product Introduction:LT1764AEFE#PBF Product Introduction

The LT1764AEFE#PBF from Analog Devices (formerly Linear Technology) is a 3A fast transient response low-dropout linear regulator optimized for noise-sensitive, high-current applications. The adjustable version allows the output voltage to be set from 1.21V to 20V using an external resistor divider. The 40uVRms output noise over 0.1Hz to 100kHz is exceptionally low for a 3A regulator, making it ideal for powering high-resolution data converters and RF circuitry. The 340mV dropout voltage at 3A enables efficient post-regulation of switching supply outputs. An external resistor programs the current limit threshold, providing flexibility for different load requirements. The TSSOP-16E package with exposed die pad provides excellent thermal dissipation for the 3A output current. The device is stable with just 10uF of ceramic output capacitance.

Working Principle:LT1764AEFE#PBF Working Principle

The LT1764A uses a PNP pass transistor in a series-pass linear regulator topology with an internal 1.21V bandgap reference. The error amplifier compares the FB pin voltage with the reference and drives the PNP pass transistor base to maintain the set output voltage. The 340mV dropout at 3A is achieved by operating the PNP transistor in saturation, requiring minimal headroom. The low output noise is achieved through internal RC filtering of the bandgap reference. The externally programmable current limit uses a sense resistor between the OUT and SENSE pins; when the voltage across this resistor exceeds 50mV (typical), the current limit amplifier reduces the pass transistor drive. Thermal shutdown disables the pass transistor when junction temperature exceeds approximately 165°C. The exposed pad on the TSSOP-16E package must be soldered to the PCB ground plane for proper thermal performance.

Pin Description:LT1764AEFE#PBF Pin Definition and Functions

Pin	Name	Function
1	OUT	Regulated output voltage (high current path)
2	SENSE	Output sense for regulation and current limit
3	ADJ	Adjustment input – connect resistor divider from output
4	GND	Ground
5	SHDN	Shutdown – pull low to disable
6	IN	Input supply voltage (2.7V-20V)
7-16	GND/NC	Ground and no-connect pins
Pad	GND	Exposed thermal pad – solder to PCB ground plane

Application Scenarios:In which products and applications isLT1764AEFE#PBF used

FPGA Core Voltage Post-Regulation: 3A current supports Virtex/UltraScale core rails; 40uVRms noise cleans switching supply ripple for FPGA PLL stability
High-Speed ADC Power: Low noise preserves 14-16 bit ADC SNR; fast transient response handles ADC sampling current transients
RF Power Amplifier Bias: Adjustable output sets PA bias voltage precisely; programmable current limit protects PA under fault conditions
Post-Regulation After SMPS: 340mV dropout enables efficient 3.3V-to-2.5V or 5V-to-3.3V post-regulation with minimal power dissipation

Alternative Models:What chips are recommended as replacements for LT1764AEFE#PBF

Model	Manufacturer	Key Difference
LT1764AEFE-1.8#PBF	ADI	Fixed 1.8V output version
LT1764AEFE-3.3#PBF	ADI	Fixed 3.3V output version
LT1963AEFE#PBF	ADI	1.5A version, same family
TPS7A4701RGWR	TI	1A, 3.8uVRms noise, VQFN-20
ADM7154ACPZ	ADI	600mA, 1uVRms noise, LFCSP-8