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HEF4094BT653

8-bit shift register with latches and tri-state outputs, 3-15V, SOIC-16, cascadable

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Manufacturer Part：

HEF4094BT653

Package：

SOIC-16 (9.9 x 3.9 x 1.5mm)

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Description

Product Overview

The HEF4094BT653 from Nexperia is an 8-stage serial shift register with output latches and tri-state outputs. It features separate shift and storage register clocks and a serial output for cascading in an SOIC-16 package.

Key Specifications

Function 8-bit serial-in/parallel-out shift register with latches
Supply Voltage 3V to 15V
Shift Clock Frequency Up to 10MHz at 10V
Output Current +/-6.8mA at 5V
Propagation Delay 60ns at 10V
Operating Temperature -40 to 125 C
Package SOIC-16

Features

  • 8-bit shift register with separate output latches
  • Tri-state outputs for bus connection
  • Serial output (Qs) for cascading
  • Strobe input for parallel data transfer
  • Wide 3V to 15V supply range

Applications

  • LED display driving
  • GPIO expansion via serial interface
  • Industrial control output modules
  • Cascaded shift register chains
  • Relay and solenoid driver control

The HEF4094BT653 from Nexperia is an 8-stage serial shift register with storage registers and tri-state outputs. It features separate clock inputs for the shift register (CP) and storage register (STR), allowing new data to be shifted in without disturbing the current output state. The tri-state outputs (OE control) enable bus-oriented applications, and the serial output (Qs) provides cascading capability for unlimited output expansion. Operating from 3V to 15V, it is compatible with both CMOS and TTL logic levels.

The HEF4094BT653 combines a serial shift register with parallel output latches and tri-state buffers. **Shift Register**: Serial data on the D input is clocked into the 8-bit shift register on each rising edge of CP (shift clock). The Qs output provides the serial overflow for cascading to the next device. **Storage Register**: On the rising edge of STR (strobe), the current shift register contents are transferred to the 8-bit storage/latch register. This two-stage architecture allows simultaneous update of all outputs. **Output Enable**: The OE input controls the tri-state output buffers. When OE is HIGH, the outputs are active; when LOW, all outputs are high-impedance. This enables direct connection to data buses. **Cascading**: The Qs serial output connects to the D input of the next device, allowing unlimited cascading. The Qs output is not tri-stated and is always active, enabling the shift clock to propagate data through the entire chain.

Pin Name Description
1 STR Strobe input (latch clock)
2 CP Clock pulse input (shift clock)
3 D Serial data input
4 OE Output enable (active high)
5-12 Q0-Q7 Parallel outputs (tri-state)
13 Q7S Serial cascade output
14 QS Serial cascade output (inverted timing)
15 VSS Ground
16 VDD Power supply (3-15V)
  • LED Display: Driving 7-segment or LED matrix displays from microcontroller serial output
  • GPIO Expansion: Adding 8+ digital outputs using only 3 MCU pins (D, CP, STR)
  • Industrial Control: Cascaded output modules for PLC relay and solenoid driving
  • Home Automation: Multi-channel light and appliance control via serial chain
  • Instrumentation: Digital front panel indicator and control output driving
Model Manufacturer Key Difference
CD4094BE TI Same function, DIP-16
74HC4094D Nexperia 2-6V HC family, faster speed
74HCT4094D Nexperia TTL-compatible inputs, HC family
MC14094BDR2G onsemi Same function, SOIC-16
74HC595D Nexperia Similar but more common, different pinout
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