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FDMC2523P

P-ch MOSFET, -60V, -6A, 120mOhm @-10V, Power56 DPAK-5

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Manufacturer Part：

FDMC2523P

Package：

Power56 / DPAK-5 (6.5 x 5.0 x 2.3 mm)

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Description

Product Overview

The FDMC2523P is a P-channel enhancement mode power trench MOSFET from onsemi with -60V VDSS, -6A ID, and 120 mΩ RDS(ON) max at VGS=-10V in a compact Power56 (DPAK-5) surface-mount package.

Key Specifications

Channel Type P-Channel Enhancement
Drain-Source Voltage (VDSS) -60 V
Continuous Drain Current -6 A (at TC=25°C)
RDS(ON) max 120 mΩ @ VGS=-10V
RDS(ON) max 180 mΩ @ VGS=-4.5V
Gate Threshold Voltage -1.0 V to -2.5 V
Total Gate Charge 12 nC typical
Power Dissipation 2.5 W (at TA=25°C)
Operating Temperature -55°C to +150°C (Tj)
Package Power56 / DPAK-5

Features

  • P-channel power trench MOSFET
  • Low RDS(ON): 120 mΩ @ VGS=-10V
  • 60V drain-source voltage rating
  • 6A continuous drain current
  • Low gate charge: 12 nC typical
  • Compact Power56 (DPAK-5) surface-mount package
  • Logic-level gate drive compatible
  • 100% avalanche tested

Applications

  • Load switches and power management
  • Battery protection circuits
  • Reverse polarity protection
  • DC-DC converters (high-side switch)
  • Motor and solenoid drives

The FDMC2523P is a P-channel enhancement mode power trench MOSFET from onsemi designed for low-voltage power management applications. Using trench technology, it achieves low on-resistance of 120 mΩ at VGS=-10V while maintaining low gate charge of 12 nC for efficient switching. The -60V drain-source rating and -6A continuous current make it suitable for high-side load switching, battery protection, and DC-DC converter applications. The compact Power56 (DPAK-5) package provides good thermal performance in a surface-mount footprint. Logic-level gate drive capability allows direct drive from 3.3V or 5V microcontroller GPIO pins.

The FDMC2523P is a P-channel MOSFET where current flows from source to drain when the gate voltage is pulled below the source (negative VGS). The trench MOSFET structure uses vertical trenches etched into the silicon with gate oxide and polysilicon filling, creating a channel on the trench sidewalls. This provides higher cell density and lower RDS(ON) than planar structures. When VGS exceeds the threshold (more negative than -1.0V to -2.5V), an inversion layer forms along the trench sidewalls, connecting the P+ source to the P-epi drain region and allowing current flow. The low gate charge (12 nC) minimizes the energy required to switch the device, reducing driver power dissipation. As a P-channel device, it can be used as a high-side switch without the charge pump or bootstrap circuit required by N-channel MOSFETs.

Pin Name Type Description
1 Source Power Source terminal (connected to VIN in high-side config)
2 Drain Power Drain terminal (connected to load)
3 Gate Input Gate control terminal
4 Source Power Source terminal (mirror)
5 Drain Power Drain terminal (mirror)
Tab Drain Power Thermal pad connected to drain
  • High-Side Load Switch: P-channel eliminates charge pump; 120 mΩ RDS(ON) minimizes voltage drop at 6A loads
  • Battery Protection: -60V rating provides margin for 48V battery systems; low RDS(ON) extends battery life
  • Reverse Polarity Protection: Gate tied to ground, source to supply — blocks reverse current automatically
  • DC-DC Converters: Low gate charge (12 nC) enables efficient high-frequency buck/boost switching
  • Power Routing: Logic-level gate drive from 4.5V MCU GPIO for battery-powered power path management
Model Manufacturer Key Difference
FDMC2583P onsemi -60V, -8.2A, 78 mΩ, higher current
FDS6575 onsemi -30V, -12A, 18 mΩ, lower voltage
IRF9Z34NPBF Infineon -60V, -5.5A, 140 mΩ, DPAK-3
SI2333DS-T1-GE3 Vishay -30V, -4.1A, 38 mΩ, SOT-23
AOD4185 Alpha & Omega -40V, -10A, 28 mΩ, DPAK
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Contact Information

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Tel / WhatsApp: +86 13760382860

Service & Packaging

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Tel / WhatsApp: +86 13760382860
Address: Room 2919, Guoli Building, Huaqiang North, Futian District, Shenzhen, Guangdong, China
 

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