74HCT138D


3-to-8 decoder/demux, TTL inputs, active-LOW outputs, SOIC-16

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Pieza del fabricante:

74HCT138D

Paquete:

SOIC-16 / SOT109-1 (9.9×3.9×1.45 mm, 1.27mm pitch)

Marca:
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Descripción

Productos

The 74HCT138D from Nexperia is a 3-to-8 line decoder/demultiplexer with TTL-compatible input levels in an SOIC-16 package. It decodes three binary-weighted address inputs (A0-A2) to eight mutually exclusive active-LOW outputs (Y0-Y7). Three enable inputs (E1, E2 active-LOW; E3 active-HIGH) allow easy parallel expansion to 1-of-32 decoding with just four ICs and one inverter.

Especificaciones

Logic Function 3-to-8 line decoder/demultiplexer (inverting outputs)
Tensión de alimentación 4.5V to 5.5V (HCT)
Retardo de propagación 19 ns typical @ 5V
Output Drive ±4 mA
Address Inputs 3 (A0, A1, A2)
Outputs 8 (Y0-Y7, active-LOW, mutually exclusive)
Enable Inputs E1, E2 (active-LOW), E3 (active-HIGH)
Input Levels TTL (74HCT138)
Temperatura de funcionamiento -40°C to +125°C
Paquete SOIC-16 (SOT109-1, 9.9×3.9 mm)

Características

  • Decodes 3 binary inputs to 8 mutually exclusive active-LOW outputs
  • Three enable inputs for easy cascading and expansion
  • Expandable to 1-of-32 decoder with four ‘138 ICs + one inverter
  • Can serve as 1-to-8 demultiplexer using enable as data input
  • Ideal for memory chip-select decoding
  • TTL-compatible input levels
  • Input clamp diodes for overvoltage interface

Aplicaciones

  • Memory chip-select decoding in microprocessor systems
  • I/O port address decoding
  • Data demultiplexing and distribution
  • 1-of-N decoder expansion in digital systems

The 74HCT138D from Nexperia is a 3-to-8 line decoder/demultiplexer with TTL-compatible inputs in an SOIC-16 package. Decoding three address inputs to eight active-LOW mutually exclusive outputs, with three enable inputs for cascading expansion to 1-of-32 decoding. Ideal for memory chip-select decoding, I/O port addressing, and data demultiplexing in 5V microprocessor systems.

The 74HCT138D decodes three binary-weighted address inputs (A0, A1, A2) to activate one of eight active-LOW outputs (Y0-Y7). The selected output goes LOW while all others remain HIGH. Three enable inputs control the device: E1 and E2 are active-LOW, E3 is active-HIGH. The device is enabled only when E1=LOW, E2=LOW, and E3=HIGH. This triple-enable scheme enables easy cascading; for example, four 74HCT138Ds with a single inverter can create a 5-to-32 line decoder (1-of-32). The device can also function as a 1-to-8 demultiplexer by using one active-LOW enable as a data input and the remaining enables as strobes, routing data to the selected output. The TTL-compatible input stage accepts standard 5V logic levels directly.

Pin Nombre Tipo Función
1 A0 Entrada Address input LSB (TTL level)
2 A1 Entrada Address input
3 A2 Entrada Address input MSB
4 E1 Entrada Enable input (active LOW)
5 E2 Entrada Enable input (active LOW)
6 E3 Entrada Enable input (active HIGH)
7 Y7 Salida Decoded output (active LOW)
8 GND Potencia Tierra (0V)
9 Y6 Salida Decoded output
10 Y5 Salida Decoded output
11 Y4 Salida Decoded output
12 Y3 Salida Decoded output
13 Y2 Salida Decoded output
14 Y1 Salida Decoded output
15 Y0 Salida Decoded output
16 VCC Potencia Supply voltage (4.5-5.5V)
  • Memory chip-select decoding in 5V microprocessor systems
  • I/O port address decoding and peripheral selection
  • Data demultiplexing: routing serial data to one of eight outputs
  • 1-of-32 decoder expansion using four 74HCT138Ds
Fabricante Número de pieza Paquete Notas
Nexperia 74HC138D SOIC-16 CMOS input levels (2.0-6.0V)
TI SN74HCT138DR SOIC-16 Functionally equivalent
ON Semi MC74HCT138ADR2G SOIC-16 Functionally equivalent
Nexperia 74HCT138PW TSSOP-16 Smaller footprint
Nexperia 74HC238D SOIC-16 Active-HIGH output version
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