Home > Integrated Circuits ICs > CD4076BE

CD4076BE

4-bit D register, 3-state outputs, input/output disable, CMOS 3-18V, PDIP-16

2000

Effective Inventory

Go to Inquiry

Image for reference only

Manufacturer Part：

CD4076BE

Package：

PDIP-16 (19.3 x 9.4 x 4.57mm, 2.54mm pitch, through-hole)

Brand：

Product Categories：

Integrated Circuits ICs, Interface ICs

Other recommendations you may be interested in.

SII9396SCNUC-BAR

IS43TR16256BL-125KBLI

Description

Product Overview

The CD4076BE from Texas Instruments is a 4-bit D-type register with 3-state outputs and input/output disable controls — a registered bus transceiver for multi-master bus systems in a 16-pin PDIP package.

Key Specifications

Function	4-bit D-type register with 3-state outputs
Technology	CD4000B CMOS
Supply Voltage	3V to 18V
Register Bits	4
Clock	Positive edge triggered
Data Disable	DI1, DI2 (both LOW = data enabled; any HIGH = input forced LOW)
Output Disable	DO1, DO2 (both LOW = outputs enabled; any HIGH = high-Z)
Clear	Asynchronous, active-HIGH (RST)
Propagation Delay	200ns typical @ VDD=10V
Operating Temperature	-55°C to +125°C
Package	PDIP-16 (19.3 x 9.4mm)

Features

4-bit edge-triggered D register
3-state outputs for bus connection
Independent input and output disable controls
Asynchronous clear
3V-18V wide supply range

Applications

Bus registers
I/O port latches
Data buffering with bus isolation
Multi-master bus systems

Product Introduction:CD4076BE Product Introduction

The CD4076BE from Texas Instruments is a 4-bit edge-triggered D register with 3-state outputs and separate input/output disable controls. It captures 4 bits of data on the rising clock edge and holds them until the next clock. The 3-state outputs allow multiple CD4076 registers to share a common bus — only one register drives the bus at a time. The input disable (DI1, DI2) controls what gets loaded: when both DI1 and DI2 are LOW, the D inputs pass through normally; when either DI1 or DI2 is HIGH, the inputs are forced LOW internally (zeros are loaded on the next clock). This allows one input to serve as a data enable while the other provides a zero-load function. The output disable (DO1, DO2) controls the 3-state outputs: when both are LOW, outputs drive the bus; when either is HIGH, outputs go to high-impedance. The two disable inputs each provide independent gating, allowing flexible control logic. The asynchronous clear (RST=HIGH) resets all flip-flops to 0. The BE suffix denotes the PDIP-16 package.

Working Principle:CD4076BE Working Principle

The CD4076BE captures data on the rising edge of CLK. On each rising CLK edge, the D0-D3 inputs (after input disable gating) are stored in the four D flip-flops. The stored data appears on Q0-Q3 when the output enables are active (both DO1 and DO2 LOW). Input disable: DI1 and DI2 are ANDed (both must be LOW for data to pass). If either DI1 or DI2 is HIGH, the internal data path is forced to 0 — zeros are loaded on the next clock instead of the D inputs. This is useful for selectively loading data or clearing the register via clock. Output disable: DO1 and DO2 are ANDed (both must be LOW for outputs to drive). If either DO1 or DO2 is HIGH, Q0-Q3 go to high-impedance (disconnected from the bus). Multiple CD4076 registers can share a bus; only one has its outputs enabled at a time (controlled by a decoder driving DO1 or DO2). Clear: RST=HIGH asynchronously resets all flip-flops to 0, regardless of CLK, D inputs, or disable controls.

Pin Description:CD4076BE Pin Definition and Functions

Pin	Name	Type	Description
1	DO1	Input	Output disable 1 (HIGH = outputs high-Z)
2	Q0	Output	Register output bit 0 (3-state)
3	Q1	Output	Register output bit 1 (3-state)
4	DO2	Input	Output disable 2 (HIGH = outputs high-Z)
5	D0	Input	Register data input bit 0
6	D1	Input	Register data input bit 1
7	RST	Input	Asynchronous reset (active HIGH)
8	VSS	Power	Ground
9	CLK	Input	Clock (positive edge triggered)
10	DI1	Input	Data input disable 1 (HIGH = force input LOW)
11	DI2	Input	Data input disable 2 (HIGH = force input LOW)
12	D2	Input	Register data input bit 2
13	D3	Input	Register data input bit 3
14	Q2	Output	Register output bit 2 (3-state)
15	Q3	Output	Register output bit 3 (3-state)
16	VDD	Power	Supply (3V to 18V)

Application Scenarios:In which products and applications isCD4076BE used

Bus Register: 4-bit bus data → D0-D3; CLK captures data; DO1/DO2 from address decoder; only selected register drives bus
I/O Port: MCU writes data → D0-D3 with CLK; MCU reads → Q0-Q3 with DO enable; DI1 used as write enable; bidirectional I/O port
Multi-Port Register: Two CD4076s share output bus; one reads port A, other reads port B; address decoder selects which drives bus via DO
Zero-Load: DI1 = load enable (LOW=load data, HIGH=load zeros); DI2 = tied LOW; selectively load data or clear register via clock

Alternative Models:What chips are recommended as replacements for CD4076BE

Model	Manufacturer	Key Difference	Package	Supply
CD4076BM	TI	SOIC-16 surface-mount version with identical logic function and 3-18V range	SOIC-16	3-18V
CD4076BE	TI	Through-hole DIP version for prototyping and legacy board repair	DIP-16	3-18V
HEF4076BT	NXP	Pin-compatible CMOS version with improved ESD protection and 3-15V supply	SOIC-16	3-15V
MC144076BDR2G	onsemi	Pin-compatible equivalent with RoHS compliance and AEC-Q100 automotive option	SOIC-16	3-18V
74LS173D	TI/Nexperia	HC CMOS version with higher speed and 2-6V supply for modern logic systems	SOIC-16	2-6V
74LS173N	TI/Nexperia	HC CMOS through-hole version for prototyping with 2-6V supply range	DIP-16	2-6V
74LS173D	Nexperia	HCT version with TTL-compatible inputs for mixed 5V TTL/CMOS systems	SOIC-16	4.5-5.5V

CD4076 is the CMOS 4000-series 4-bit register with 3-state operating over the wide 3-18V supply range. The HEF4076 (NXP) and MC144076 (onsemi) are direct pin-compatible equivalents. For higher speed at the cost of narrower voltage range, the 74LS173 HC/HCT families offer significantly faster propagation delay and lower power consumption at 2-6V. Surface-mount versions use the BM/M suffix (SOIC); through-hole versions use the BE suffix (DIP).