Home > Integrated Circuits ICs > CD4042BE

CD4042BE

Quad clocked D latch, polarity control, complementary outputs, CMOS 3-18V, PDIP-16

4000

Effective Inventory

Go to Inquiry

Image for reference only

Manufacturer Part：

CD4042BE

Package：

PDIP-16 (19.3 x 9.4 x 4.57mm, 2.54mm pitch, through-hole)

Brand：

Product Categories：

Integrated Circuits ICs, Interface ICs

Other recommendations you may be interested in.

SII9396SCNUC-BAR

IS43TR16256BL-125KBLI

Description

Product Overview

The CD4042BE from Texas Instruments is a quad clocked D-type latch with clock polarity control and complementary outputs — four transparent latches in a single 16-pin PDIP package that can be configured for either level-triggered mode.

Key Specifications

Function	Quad clocked D latch (4 transparent latches)
Technology	CD4000B CMOS
Supply Voltage	3V to 18V
Number of Latches	4 (independent D inputs, common CLK)
Clock Polarity	Programmable via POLARITY input
Outputs	Q and Q̄ per latch (complementary, buffered)
Propagation Delay	500ns typical @ VDD=5V; 150ns @ 10V
Max Clock Frequency	8MHz @ VDD=10V
Output Current	2.4mA sink / 2.4mA source @ VDD=10V
Operating Temperature	-55°C to +125°C
Package	PDIP-16 (19.3 x 9.4mm)

Features

Four D-type latches with common clock
Clock polarity control (active-HIGH or active-LOW clock)
Complementary Q and Q̄ outputs from each latch
Transparent mode: outputs follow D while clock is active
Latched mode: outputs hold when clock transitions
3V-18V wide supply range

Applications

Buffer storage / data holding registers
Address latches for multiplexed buses
Debouncing circuits
General digital storage

Product Introduction:CD4042BE Product Introduction

The CD4042BE from Texas Instruments contains four D-type transparent latches with a common clock and a unique polarity control input. The POLARITY pin determines whether the latches are transparent when CLOCK is LOW (POLARITY=0) or when CLOCK is HIGH (POLARITY=1). When the clock is at the ‘active’ level (as defined by POLARITY), the Q outputs follow their respective D inputs (transparent mode). When the clock transitions away from the active level, the data present at the D inputs at that moment is latched and held at the Q outputs until the next active clock phase. Each latch provides both Q and Q̄ (complementary) outputs, all fully buffered with balanced CMOS push-pull drivers. The common clock simplifies system design when all four latches must capture data simultaneously (e.g., address latching for multiplexed address/data buses). The polarity feature eliminates the need for an external inverter: if the system clock is active-HIGH, set POLARITY=1; if active-LOW, set POLARITY=0. The 3V-18V supply range covers all common digital voltage levels. The BE suffix denotes the PDIP-16 package.

Working Principle:CD4042BE Working Principle

Each of the four latches in the CD4042BE operates as a transparent D latch with the following behavior controlled by the CLOCK and POLARITY inputs. When POLARITY=0: the latches are transparent when CLOCK=LOW (Q follows D while CLOCK is LOW). When CLOCK transitions from LOW to HIGH (rising edge), the D input value is captured and held. When POLARITY=1: the latches are transparent when CLOCK=HIGH (Q follows D while CLOCK is HIGH). When CLOCK transitions from HIGH to LOW (falling edge), the D input value is captured and held. In both cases, the opposite clock transition re-enables transparency. This is summarized as: the data is transferred to the outputs during the clock level equal to the POLARITY value, and latched on the opposite clock edge. The Q̄ output always provides the complement of Q. The four latches share the same CLOCK and POLARITY inputs, so they all operate in the same mode simultaneously. For address latching in a multiplexed bus system: the address appears on the bus during the active clock phase; the CD4042 captures it on the inactive transition; the latched address is stable while data occupies the bus.

Pin Description:CD4042BE Pin Definition and Functions

Pin	Name	Type	Description
1	Q4	Output	Latch 4 complementary output (Q̄4)
2	Q1	Output	Latch 1 true output (Q1)
3	Q̄1	Output	Latch 1 complementary output (Q̄1)
4	D1	Input	Latch 1 data input
5	CLOCK	Input	Common clock (all 4 latches)
6	POLARITY	Input	Clock polarity (0=transparent on LOW, 1=transparent on HIGH)
7	D2	Input	Latch 2 data input
8	VSS	Power	Ground
9	Q̄2	Output	Latch 2 complementary output (Q̄2)
10	Q2	Output	Latch 2 true output (Q2)
11	Q̄3	Output	Latch 3 complementary output (Q̄3)
12	Q3	Output	Latch 3 true output (Q3)
13	D3	Input	Latch 3 data input
14	D4	Input	Latch 4 data input
15	Q̄4	Output	Latch 4 complementary output (Q̄4)
16	VDD	Power	Supply (3V to 18V)

Application Scenarios:In which products and applications isCD4042BE used

Address Latch: Multiplexed address/data bus → D1-D4; ALE signal → CLOCK; POLARITY=1 (transparent when HIGH); address captured on falling ALE edge; stable address for external memory
Data Hold Register: Sensor data → D1-D4; sample pulse → CLOCK; POLARITY=0; data captured on rising clock edge; held between samples
Debouncer: Switch → D1; oscillator → CLOCK; POLARITY=1; switch state sampled at clock rate; output free of bounce
4-Bit Comparator Storage: CD4063 comparator outputs → D1-D4; clock latches comparison result; Q outputs held for next processing stage

Alternative Models:What chips are recommended as replacements for CD4042BE

Model	Manufacturer	Key Difference	Package	Supply
CD4042BM	TI	SOIC-16 surface-mount version with identical logic function and 3-18V range	SOIC-16	3-18V
CD4042BE	TI	Through-hole DIP version for prototyping and legacy board repair	DIP-16	3-18V
HEF4042BT	NXP	Pin-compatible CMOS version with improved ESD protection and 3-15V supply	SOIC-16	3-15V
MC144042BDR2G	onsemi	Pin-compatible equivalent with RoHS compliance and AEC-Q100 automotive option	SOIC-16	3-18V
74LS75D	TI/Nexperia	HC CMOS version with higher speed and 2-6V supply for modern logic systems	SOIC-16	2-6V
74LS75N	TI/Nexperia	HC CMOS through-hole version for prototyping with 2-6V supply range	DIP-16	2-6V
74LS75D	Nexperia	HCT version with TTL-compatible inputs for mixed 5V TTL/CMOS systems	SOIC-16	4.5-5.5V

CD4042 is the CMOS 4000-series quad clocked d latch operating over the wide 3-18V supply range. The HEF4042 (NXP) and MC144042 (onsemi) are direct pin-compatible equivalents. For higher speed at the cost of narrower voltage range, the 74LS75 HC/HCT families offer significantly faster propagation delay and lower power consumption at 2-6V. Surface-mount versions use the BM/M suffix (SOIC); through-hole versions use the BE suffix (DIP).