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CD4013BE

Dual D flip-flop, 3-15V CMOS, async S/R, 10MHz toggle, PDIP-14

8500

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Manufacturer Part：

CD4013BE

Package：

PDIP-14 (19.3 x 6.35 x 4.57mm, 2.54mm pitch)

Brand：

Product Categories：

Integrated Circuits ICs, Interface ICs

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Description

Product Overview

The CD4013BE is a dual D-type flip-flop from Texas Instruments with independent set and reset, static and clocked operation, and 10MHz typical toggle frequency in a 14-pin PDIP package.

Key Specifications

Number of Flip-Flops	2 (dual, independent)
Supply Voltage Range	3V to 15V
Toggle Frequency	10MHz typical at 10V, 4MHz at 5V
Clock Pulse Width	40ns typical at 10V
Setup Time	15ns typical at 10V
Hold Time	5ns typical at 10V
Input Current	1µA typical at 10V
Output Drive	1.3mA sink/source at 5V
Quiescent Current	2µA typical per package at 5V
Set/Reset	Active high, independent, asynchronous
Operating Temperature	-55°C to +125°C
Package	PDIP-14 (19.3 x 6.35mm, through-hole)

Features

Two independent D-type flip-flops in one package
Asynchronous set (S) and reset (R) inputs, active high
Data transfers to output on positive clock edge
Wide supply voltage range: 3V to 15V
Standard CMOS input and output levels
Very low quiescent current: 2µA typical at 5V
Military temperature range: -55°C to +125°C
Direct replacement for CD4013 and MC14013

Applications

Frequency dividers and counters
Shift registers and data storage
Toggle flip-flops for timing circuits
Control and sequencing logic
Debouncing and synchronization circuits

Product Introduction:CD4013BE Product Introduction

The CD4013BE is a dual D-type flip-flop from Texas Instruments in the 4000B CMOS logic family. Each flip-flop has independent data (D), clock (CL), set (S), and reset (R) inputs, and complementary outputs (Q and Q-bar). Data on the D input is transferred to the Q output on the positive-going edge of the clock pulse. The set and reset inputs are asynchronous and active-high, overriding the clocked operation when asserted. The device operates over a wide 3V to 15V supply range with very low 2µA quiescent current, making it suitable for battery-powered and industrial applications. The military temperature range (-55°C to +125°C) ensures reliable operation in harsh environments.

Working Principle:CD4013BE Working Principle

The CD4013BE implements two independent edge-triggered D-type flip-flops using CMOS transmission gates and inverters. Each flip-flop consists of a master-slave latch configuration controlled by the clock signal. When the clock is low, the master latch is transparent (accepts D input) and the slave latch is isolated (holds previous Q). On the rising clock edge, the master latch becomes isolated (capturing D) and the slave latch becomes transparent (transferring master state to Q). This master-slave arrangement ensures that data is captured on the rising edge and held stable through the clock cycle. The asynchronous set input forces Q high and Q-bar low regardless of the clock and D inputs, while the reset input forces Q low and Q-bar high. When both S and R are asserted simultaneously, both Q and Q-bar go high (invalid state), and the final output state when both are released is indeterminate. The CMOS transmission gates use complementary NMOS/PMOS pairs that pass the full logic swing, enabling rail-to-rail output levels.

Pin Description:CD4013BE Pin Definition and Functions

Pin	Name	Type	Description
1	Q1	Output	Flip-flop 1 true output
2	Q1-bar	Output	Flip-flop 1 complement output
3	CL1	Input	Flip-flop 1 clock (rising edge triggered)
4	R1	Input	Flip-flop 1 reset (active high, asynchronous)
5	D1	Input	Flip-flop 1 data input
6	S1	Input	Flip-flop 1 set (active high, asynchronous)
7	VSS	Power	Ground (0V)
8	S2	Input	Flip-flop 2 set (active high, asynchronous)
9	D2	Input	Flip-flop 2 data input
10	R2	Input	Flip-flop 2 reset (active high, asynchronous)
11	CL2	Input	Flip-flop 2 clock (rising edge triggered)
12	Q2-bar	Output	Flip-flop 2 complement output
13	Q2	Output	Flip-flop 2 true output
14	VDD	Power	Supply voltage (3V-15V)

Application Scenarios:In which products and applications isCD4013BE used

Frequency Division: Connect Q-bar to D to form a toggle flip-flop that divides the clock frequency by 2
Shift Registers: Cascade D flip-flops by connecting Q to the next D input for serial data storage and transfer
Debouncing: D input connected to VDD with a clocked push-button creates a clean, debounced toggle output
Control Sequencing: Set and reset inputs provide asynchronous control for state machine initialization and override
Data Synchronization: Captures asynchronous input data on clock edge for synchronous processing in digital systems

Alternative Models:What chips are recommended as replacements for CD4013BE

Model	Manufacturer	Key Difference	Package	Voltage
CD4013BM	TI	SOIC-14 surface-mount version with identical dual D-type flip-flop functionality	SOIC-14	3-18V
HEF4013BT	NXP	Pin-compatible CMOS version with wide 3-15V supply and improved ESD protection	SOIC-14	3-15V
MC14013BDR2G	onsemi	Pin-compatible equivalent with automotive AEC-Q100 qualified variant available	SOIC-14	3-18V
74HC74D	NXP	HC CMOS dual D-FF with higher speed (50MHz typ) and 2-6V supply range	SOIC-14	2-6V
SN74LVC2G74DCUR	TI	Single D-FF in tiny VSSOP-8, 1.65-5.5V for low-voltage logic systems	VSSOP-8	1.65-5.5V
74AUP2G74GWH	Nexperia	Ultra-low power dual D-FF with 0.8-3.6V supply for battery-powered designs	XSON-10	0.8-3.6V

CD4013BE is the industry-standard CMOS dual D-type flip-flop with independent Set, Reset, Clock, and Data inputs. HC74 versions offer higher speed at the cost of narrower voltage range. For modern low-voltage designs, LVC2G74 operates down to 1.65V.