AT24C04C-SSHM-B

The AT24C04C from Microchip (originally Atmel) is a 4 Kbit I2C serial EEPROM organized as 512 x 8 bits. The AT24C04C-SSHM-B is the SOIC-8 tube-packaged version for the -40°C to +85°C industrial temperature range. It is part of the AT24CxxC family, which also includes the AT24C01C (1 Kbit), AT24C02C (2 Kbit), and AT24C08C (8 Kbit) with identical pinouts and protocols.

The device supports two I2C speed modes: Standard-mode (400 kHz) at 1.7 V and Fast-mode Plus (1 MHz) at 2.5 V and above. The 16-byte page write buffer allows writing up to 16 bytes in a single I2C transaction, after which the internal write cycle completes in 5 ms maximum. Random and sequential read modes support single-byte and continuous read operations.

The hardware write-protect pin (WP) protects the entire memory array when pulled HIGH, preventing accidental or malicious writes. This is useful for calibration data, serial numbers, and configuration parameters that must not change in the field.

Three address pins (A0, A1, A2) allow up to four AT24C04C devices to share the same I2C bus, providing a total of 16 Kbit of EEPROM on a single bus. The device uses the standard Atmel I2C EEPROM protocol with a 7-bit slave address (1010 + A2A1A0 + R/W).

The 1.7 V minimum supply voltage enables direct operation from single-cell Li-ion batteries (2.7-4.2 V) and 1.8 V logic systems. The 6 µA maximum standby current preserves battery life in always-connected applications.

An automotive-qualified version (AT24C04C-STPD-TVAO, AEC-Q100 Grade 1, -40°C to +125°C) is available for automotive applications.

**I2C Interface Protocol:** The AT24C04C communicates via the standard I2C protocol. The master initiates communication with a START condition, followed by the 7-bit device address (1010 + A2A1A0) and a R/W bit. The EEPROM acknowledges (ACK) by pulling SDA low on the 9th clock. Data is transferred MSB first, 8 bits per byte, with ACK after each byte.

**Write Operation:** For byte write, the master sends device address + write, then the 8-bit word address, then data byte, then STOP. The EEPROM enters an internal write cycle (5 ms max) during which it does not respond to I2C commands. Page write works similarly but accepts up to 16 data bytes; the lower 4 address bits auto-increment and wrap within the page.

**Read Operation:** Random read requires a dummy write sequence (device address + write, word address, RESTART, device address + read) to set the address counter, then data is clocked out. Current address read starts from the last accessed address + 1. Sequential read continues indefinitely until the master sends NACK + STOP.

**Memory Cell Technology:** The EEPROM uses floating-gate MOS transistors. Write operations inject charge onto the floating gate via Fowler-Nordheim tunneling through a thin oxide layer. Erase removes the charge. The high-quality oxide provides 100-year data retention and 1 million cycle endurance.