TPS7333QDR

The TPS7333QDR from Texas Instruments is a 500mA low-dropout voltage regulator with a fixed 3.3V output and an integrated precision supply-voltage supervisor that generates a delayed active-low reset signal. The PMOS pass element provides exceptionally low dropout voltage (44mV at 100mA) and quiescent current that remains constant at 340µA regardless of load current—from no load to full 500mA load. This is a significant advantage over PNP-based LDOs whose quiescent current increases with load. The integrated reset function monitors the output voltage; if it drops below approximately 89% of the nominal value, the open-drain RESET output goes LOW. When the output recovers, RESET remains LOW for an additional 200ms (typical) before going HIGH, ensuring the microprocessor has stable power before exiting reset. The enable pin (active-low) allows the regulator to be placed in a 0.5µA sleep mode. The QDR suffix denotes the SOIC-8 package with tape-and-reel packaging, rated for the extended -40°C to 125°C temperature range.

The TPS7333QDR uses a PMOS pass transistor between VIN and VOUT, controlled by an error amplifier that compares a fraction of the output voltage against an internal bandgap reference. When the output voltage drops below 3.3V, the error amplifier drives the PMOS gate more negative (relative to VIN), increasing the pass transistor’s channel width and allowing more current to flow to the load. When the output rises above 3.3V, the error amplifier reduces the gate drive, limiting current flow. The PMOS pass element is key to the LDO’s performance: unlike PNP transistors that require significant base current (which adds to quiescent current and varies with load), the PMOS gate draws only leakage current, so Iq stays at 340µA regardless of whether the load is 0mA or 500mA. The dropout voltage is simply ID × RDS(on) of the PMOS, which is very low (0.44Ω typical at 25°C, giving 44mV at 100mA). The reset circuit continuously monitors the output voltage through the SENSE pin. When VOUT drops below the reset threshold (approximately 2.93V for the 3.3V version), RESET goes LOW. When VOUT recovers above the threshold, an internal timer starts; after 200ms, RESET goes HIGH (open-drain releases). The EN pin controls sleep mode: when EN is HIGH, the PMOS pass element is turned off and Iq drops to 0.5µA.

TPS7333QDR uses the 8-SOIC (D) package with LDO regulator pinout: Pin 1 = GND, Pin 2 = EN (Enable, active-high), Pin 3 = IN, Pin 4 = IN, Pin 5 = NC, Pin 6 = NC, Pin 7 = SENSE/FB (3.3V fixed output senses at this pin), Pin 8 = OUT. Two IN pins must both be connected to the input supply for proper current distribution. The EN pin has a precision threshold — pull above 2V to enable, below 0.5V to disable. The SENSE pin (Pin 7) should be connected directly at the load for accurate voltage regulation (remote sensing). A 10µF ceramic output capacitor provides stability with less than 50mV output noise.

• MCU Power+Reset: Single IC provides 3.3V rail and reset signal; RESET connects to MCU /RST pin, eliminating external supervisor IC
• Battery Device: 340µA constant Iq extends battery life; EN pin enables 0.5µA sleep mode during standby
• Post-SMPS Regulator: Low 44mV dropout after 3.3V switching supply leaves minimal headroom; PSRR >49dB attenuates switcher ripple
• Hot-Plug: RESET stays LOW for 200ms after output stabilizes, preventing MCU from executing during power-up transients
• Brownout Detect: RESET asserts when 3.3V rail drops below 2.93V; MCU enters reset before SRAM data corrupts

TPS7333QDR is a 3.3V/500mA LDO from TI in SOIC-8 with PG output. The TPS7333QPWPR provides the same in TSSOP-20. The TPS7A4700 offers ultralow noise 1A LDO for RF applications. The LM1117MP-3.3 provides 800mA in smaller SOT-223. The TPS73633DBVR offers 400mA with 75mV dropout in SOT-23-5. The MCP1826T-3302E/DC provides 1A with anyCAP stability from Microchip. For higher current, TPS7A7001 offers 1A adjustable ultralow noise in VSON-10.