The STM8S105S4T6C is an 8-bit STM8 core microcontroller with 32KB Flash, 2KB RAM, and 1KB EEPROM in LQFP-44. The STM8 core uses a 3-stage pipeline (fetch, decode, execute) with a modified Harvard architecture. At 16MHz, it delivers approximately 10 MIPS. The integrated EEPROM supports 300,000 erase/write cycles for parameter storage. The 10-bit ADC supports 10 channels with conversion time of 3.5us. The 16-bit advanced control timer (TIM1) supports PWM generation with complementary outputs and dead-time insertion for motor control. The window watchdog (WWDG) and independent watchdog (IWDG) provide independent safety layers. Single-wire interface module (SWIM) enables in-circuit debugging and programming with just one pin. The device features clock security system (CSS) that automatically switches to internal RC if the external crystal fails.