الصفحة الرئيسية > الدوائر المتكاملة الدوائر المتكاملة > SN74LVC74ADR

SN74LVC74ADR

Dual D flip-flop, pos-edge, preset/clear, 1.65-3.6V, 5.2ns, SOIC-14

11200

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جزء الشركة المصنعة ： جزء الشركة المصنعة

SN74LVC74ADR

الحزمة ： الحزمة

14-Pin SOIC (8.65 x 3.91 x 1.27 mm)

العلامة التجارية ： العلامة التجارية

فئات المنتجات:：فئات المنتجات

الدوائر المتكاملة الدوائر المتكاملة, واجهة ICs

توصيات أخرى قد تكون مهتماً بها.

SII9396SCNUC-BAR

IS43TR16256BL-125KBLI

الوصف

نظرة عامة على المنتج

The SN74LVC74ADR is a Texas Instruments dual positive-edge-triggered D-type flip-flop with preset and clear in a 14-pin SOIC package. It operates from 1.65V to 3.6V with 5.5V-tolerant inputs, 5.2ns max propagation delay at 3.3V, and latch-up exceeding 250mA. Rated for -40C to +125C.

المواصفات الرئيسية

الوظيفة	Dual D flip-flop
Trigger	Positive-edge
VCC Range	1.65 V to 3.6 V
tpd (max)	5.2 ns at 3.3 V
الميزات	Preset, Clear
fmax	~150 MHz

الميزات

Dual D-type positive-edge-triggered flip-flops
Asynchronous preset and clear
1.65V to 3.6V operation
5.5V tolerant inputs
5.2ns max propagation delay
ESD: 2000V HBM, 1000V CDM
SOIC-14 package

التطبيقات

Clock division and synchronization
State machine and control logic
Data storage and transfer
Frequency synthesis

مقدمة المنتج:SN74LVC74ADR مقدمة المنتج

The SN74LVC74ADR is a Texas Instruments dual positive-edge-triggered D-type flip-flop with individual asynchronous preset (PRE, active low) and clear (CLR, active low) inputs. Each flip-flop stores one bit of data, with the Q output following the D input on the rising edge of the clock (CLK). The preset and clear inputs override the clock and data inputs, directly setting or resetting the outputs. The device operates from 1.65V to 3.6V VCC with inputs accepting voltages to 5.5V for mixed-voltage systems. The 5.2ns maximum propagation delay at 3.3V enables operation up to approximately 150 MHz. ESD protection exceeds 2000V HBM and 1000V charged-device model. Latch-up performance exceeds 250mA per JESD 17. Packaged in 14-pin SOIC rated for -40C to +125C.

مبدأ العمل:SN74LVC74ADR مبدأ العمل

Each flip-flop in the SN74LVC74A consists of a master-slave latch configuration optimized for positive-edge triggering. On the rising edge of CLK, the D input is sampled and transferred to the Q output. The asynchronous preset (PRE) and clear (CLR) inputs use internal gating logic to override the clocked operation: a low on PRE sets Q high regardless of CLK and D, while a low on CLR resets Q low. Simultaneous low on both PRE and CLR is normally prohibited as both Q and Q-bar will go high. The CMOS implementation uses transmission gates and inverters for the master and slave latches, providing low static power consumption and rail-to-rail output swing.

وصف الدبوس:SN74LVC74ADR تعريف الدبوس ووظائفه

دبوس	Mnemonic	الوصف
1	1CLR	Clear 1 (active low)
2	1D	إدخال البيانات 1
3	1CLK	Clock input 1 (rising edge)
4	1PRE	Preset 1 (active low)
5,6	1Q,1Q	Output 1, complement
7	GND	أرضي
8-13	2Q-2CLR	Flip-flop 2 (mirror)
14	VCC	Supply