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SN74LS193N

4-bit up/down binary counter, separate CU/CD, async CLR/LOAD, CO/BO, PDIP-16

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جزء الشركة المصنعة ： جزء الشركة المصنعة

SN74LS193N

الحزمة ： الحزمة

PDIP-16 (19.3 x 6.35 x 4.57mm, 2.54mm pitch, through-hole)

العلامة التجارية ： العلامة التجارية

فئات المنتجات:：فئات المنتجات

الدوائر المتكاملة الدوائر المتكاملة, واجهة ICs

توصيات أخرى قد تكون مهتماً بها.

SII9396SCNUC-BAR

IS43TR16256BL-125KBLI

الوصف

نظرة عامة على المنتج

The SN74LS193N from Texas Instruments is a 4-bit synchronous up/down binary counter with separate up and down clock inputs, asynchronous clear and load, and borrow/carry outputs for cascading in a 16-pin PDIP package.

المواصفات الرئيسية

الوظيفة	4-bit synchronous up/down binary counter
عائلة المنطق	LS (Low-power Schottky)
جهد الإمداد	4.75V to 5.25V (5V nominal)
Count Range	0 to 15 (4-bit binary)
Clock Inputs	CU (count up) and CD (count down), falling-edge triggered
Asynchronous Clear (CLR)	Active-high, resets count to 0000
Asynchronous Load (LOAD)	Active-low, loads D inputs to Q outputs
Data Inputs	D0-D3 (parallel load)
Carry Output (CO)	Goes LOW when count=15 and CU goes LOW
Borrow Output (BO)	Goes LOW when count=0 and CD goes LOW
Maximum Clock Frequency	25MHz typical
درجة حرارة التشغيل	0°C to +70°C
الحزمة	PDIP-16 (19.3 x 6.35mm)

الميزات

4-bit synchronous up/down binary counter
Separate up and down clock inputs
Asynchronous parallel load
Asynchronous clear
Carry and borrow outputs for cascading
Count in either direction independently

التطبيقات

Up/down counting
Position tracking (motor encoder)
Frequency division
Digital potentiometer control
Programmable timer/counter

مقدمة المنتج:SN74LS193N مقدمة المنتج

The SN74LS193N from Texas Instruments is a 4-bit synchronous up/down binary counter that counts from 0 to 15 in either direction. The unique feature is separate count-up (CU) and count-down (CD) clock inputs, both falling-edge triggered: a HIGH-to-LOW transition on CU increments the count, and a HIGH-to-LOW transition on CD decrements it. The unused clock input must be held HIGH. The asynchronous clear (CLR) input resets the count to 0000 when HIGH, regardless of the clocks. The asynchronous load (LOAD) input, when LOW, transfers the parallel data inputs (D0-D3) to the outputs (Q0-Q3), allowing presetting the count to any value. The carry output (CO) goes LOW when the count reaches 15 and CU goes LOW, and the borrow output (BO) goes LOW when the count reaches 0 and CD goes LOW. These outputs enable cascading: CO connects to the CU of the next stage, and BO connects to the CD of the next stage, for multi-decade or multi-digit counting. The N suffix denotes the PDIP-16 through-hole package.

مبدأ العمل:SN74LS193N مبدأ العمل

The SN74LS193N counts in binary from 0000 (0) to 1111 (15). On the falling edge of CU (count-up clock), the count increments by 1; on the falling edge of CD (count-down clock), it decrements by 1. The unused clock input must be held HIGH to prevent spurious counting. The counter wraps around: incrementing past 1111 returns to 0000, and decrementing below 0000 wraps to 1111. The carry output (CO) provides a LOW pulse when the count is 1111 and CU goes LOW; this connects to the CU input of the next higher-order counter, enabling it to count once per 16 counts of the lower counter. Similarly, the borrow output (BO) provides a LOW pulse when the count is 0000 and CD goes LOW, cascading the down-count to the next stage. The asynchronous clear (CLR) forces the count to 0000 when HIGH, regardless of clock or load inputs. The asynchronous load (LOAD) transfers D0-D3 to Q0-Q3 when LOW, allowing the count to be preset to any value. For example, loading 1001 (9) and counting up gives 6 more counts before wrapping, creating a divide-by-6 counter. The 193 is fully synchronous within each stage (all four bits change simultaneously), but cascading between stages is ripple (asynchronous).

وصف الدبوس:SN74LS193N تعريف الدبوس ووظائفه

دبوس	الاسم	النوع	الوصف
1	CO	المخرجات	Carry output (LOW when count=15 and CU=LOW)
2	CD	المدخلات	Count-down clock (falling edge triggered, hold HIGH when not counting down)
3	Q3	المخرجات	Count output bit 3 (MSB)
4	Q2	المخرجات	Count output bit 2
5	Q1	المخرجات	Count output bit 1
6	Q0	المخرجات	Count output bit 0 (LSB)
7	CU	المدخلات	Count-up clock (falling edge triggered, hold HIGH when not counting up)
8	GND	الطاقة	أرضي
9	D0	المدخلات	Parallel data input bit 0 (LSB)
10	D1	المدخلات	Parallel data input bit 1
11	D2	المدخلات	Parallel data input bit 2
12	D3	المدخلات	Parallel data input bit 3 (MSB)
13	BO	المخرجات	Borrow output (LOW when count=0 and CD=LOW)
14	CLR	المدخلات	Asynchronous clear (active HIGH, resets to 0000)
15	LOAD	المدخلات	Asynchronous load (active LOW, loads D0-D3 to Q0-Q3)
16	VCC	الطاقة	Supply (4.75V to 5.25V)

Application Scenarios:In which products and applications isSN74LS193N مستعمل

Position Counter: Motor encoder A→CU, B→CD; counts up on CW, down on CCW; Q0-Q3 = 4-bit position
8-Bit Counter: Two 193s cascaded; CO→CU of next, BO→CD of next; 0-255 count range
Divide-by-N: Load N, count up to 15; CO triggers LOAD; divides clock by (16-N)
Up/Down Timer: Load initial value; CU increments toward 15, CD decrements toward 0; BO/CO detect endpoints
Digital Pot: CU/CD from buttons; Q0-Q3 drive R-2R DAC; each press adjusts voltage up or down

Alternative Models:What chips are recommended as replacements for SN74LS193N

الطراز	الشركة المصنعة	الفرق الرئيسي	الحزمة	Supply
74LS193N	TI/Nexperia	Original TTL version with 5V-only supply, typical propagation delay 10-15ns	DIP-16	5V TTL
74LS193D	TI/Nexperia	Surface-mount SOIC version of LS with identical logic function	SOIC-16	5V TTL
74HC193D	TI/Nexperia	CMOS version with wide 2-6V supply range, lower power consumption and higher noise immunity	SOIC-16	2-6V CMOS
74HC193N	TI/Nexperia	Through-hole DIP version of HC family for prototyping and repair	DIP-16	2-6V CMOS
74HCT193D	TI/Nexperia	CMOS with TTL-compatible input levels, ideal for mixing with LS devices at 5V	SOIC-16	4.5-5.5V TTL-in
74HCT193N	TI/Nexperia	Through-hole DIP version of HCT family for prototyping and repair	DIP-16	4.5-5.5V TTL-in

The 74193 is a 4-Bit Binary Counter (Up/Down). Family variants span from the original LS TTL (5V only) to modern LVC/AUP (down to 0.8V). HC and HCT versions offer 2-6V CMOS operation with HCT providing TTL-compatible input thresholds for mixed 5V systems. CD4000-series equivalents offer the widest 3-18V supply range at the cost of lower switching speed. DIP packages (N suffix) are through-hole; SOIC (D suffix) and TSSOP are surface-mount.