الصفحة الرئيسية > الدوائر المتكاملة الدوائر المتكاملة > SN74LS193N

SN74LS193N

4-bit binary up/down counter, separate clocks, async load/clear, carry/borrow, LS TTL, PDIP-16

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جزء الشركة المصنعة ： جزء الشركة المصنعة

SN74LS193N

الحزمة ： الحزمة

PDIP-16 (19.3 x 6.35 x 4.57mm, 2.54mm pitch, through-hole)

العلامة التجارية ： العلامة التجارية

فئات المنتجات:：فئات المنتجات

الدوائر المتكاملة الدوائر المتكاملة, واجهة ICs

توصيات أخرى قد تكون مهتماً بها.

SII9396SCNUC-BAR

IS43TR16256BL-125KBLI

الوصف

نظرة عامة على المنتج

The SN74LS193N from Texas Instruments is a synchronous 4-bit binary up/down counter with separate clocks, parallel load, and clear — the binary (0-15) version of the 74192 in a 16-pin PDIP package.

المواصفات الرئيسية

الوظيفة	Synchronous 4-bit binary up/down counter
عائلة المنطق	LS (Low-power Schottky)
جهد الإمداد	4.75V to 5.25V
Count Range	0-15 (4-bit binary)
Clock Inputs	UP (count up), DOWN (count down), separate, negative-edge
Parallel Load	Asynchronous, active-LOW (LOAD)
Clear	Asynchronous, active-HIGH (CLR)
Carry/Borrow	CO (carry, active-LOW), BO (borrow, active-LOW)
الحد الأقصى لتردد الساعة	25MHz typical
درجة حرارة التشغيل	0°C to +70°C
الحزمة	PDIP-16 (19.3 x 6.35mm)

الميزات

Separate UP and DOWN clock inputs
Binary count: 0-15 up, 15-0 down
Asynchronous parallel load and clear
Carry/borrow outputs for cascading
Same pinout as SN74LS192N

التطبيقات

Binary up/down counters
Address generation
Programmable frequency dividers
Digital position tracking

مقدمة المنتج:SN74LS193N مقدمة المنتج

The SN74LS193N from Texas Instruments is a synchronous 4-bit binary up/down counter with the same architecture as the 74192 but counting in binary (0-15) instead of BCD (0-9). It features separate UP and DOWN clock inputs, asynchronous parallel load, asynchronous clear, and carry/borrow outputs. The dual-clock design means counting direction is determined by which clock receives pulses: UP counts 0→1→…→15→0; DOWN counts 15→14→…→0→15. The carry output (CO) goes LOW when the count is 15 and an UP pulse arrives; the borrow output (BO) goes LOW when the count is 0 and a DOWN pulse arrives. These outputs cascade directly to the next stage’s UP/DOWN inputs for multi-stage counters. The 74193 is identical to the 74192 in pinout and functionality — the only difference is the count modulus (16 vs 10). The 74193 is preferred when the full 0-15 range is needed, such as in address generation, binary frequency division, and digital signal processing. The N suffix denotes the PDIP-16 package.

مبدأ العمل:SN74LS193N مبدأ العمل

The SN74LS193N counts in binary (0-15) on the negative edge of the UP or DOWN clock. Counting UP: pulses on UP, DOWN must be HIGH. Sequence: 0→1→2→…→15→0 (carry). At 15, CO goes LOW on the next UP clock. Counting DOWN: pulses on DOWN, UP must be HIGH. Sequence: 15→14→…→1→0→15 (borrow). At 0, BO goes LOW on the next DOWN clock. Parallel load: LOAD=LOW loads D0-D3 into the counter asynchronously. CLR=HIGH resets to 0 asynchronously. Priority: CLR > LOAD > clocks. For multi-stage cascading: CO of stage 1 → UP of stage 2; BO of stage 1 → DOWN of stage 2. Two stages count 0-255 (8-bit); four stages count 0-65535 (16-bit). The separate UP/DOWN clocks allow independent control of increment and decrement — useful when UP and DOWN signals come from different sources (e.g., two rotary encoders, or increment/decrement buttons).

وصف الدبوس:SN74LS193N تعريف الدبوس ووظائفه

دبوس	الاسم	النوع	الوصف
1	DOWN	المدخلات	Count-down clock (negative edge, UP must be HIGH)
2	Q1	المخرجات	Output bit 1
3	Q0	المخرجات	Output bit 0 (LSB)
4	BO	المخرجات	Borrow output (active-LOW; LOW at count=0 with DOWN clock)
5	CO	المخرجات	Carry output (active-LOW; LOW at count=15 with UP clock)
6	Q3	المخرجات	Output bit 3 (MSB)
7	Q2	المخرجات	Output bit 2
8	GND	الطاقة	أرضي
9	D2	المدخلات	Parallel data input bit 2
10	D3	المدخلات	Parallel data input bit 3 (MSB)
11	D0	المدخلات	Parallel data input bit 0 (LSB)
12	D1	المدخلات	Parallel data input bit 1
13	LOAD	المدخلات	Parallel load enable (active-LOW, loads D0-D3)
14	CLR	المدخلات	Asynchronous clear (active-HIGH, resets to 0)
15	UP	المدخلات	Count-up clock (negative edge, DOWN must be HIGH)
16	VCC	الطاقة	Supply (5V)

Application Scenarios:In which products and applications isSN74LS193N مستعمل

8-Bit Binary Counter: Two 74193s; CO(#1) → UP(#2); BO(#1) → DOWN(#2); 8-bit count 0-255; cascaded carry/borrow
Programmable Divider: Preset divisor-1 on D0-D3; LOAD presets counter; count down to 0; BO reloads preset; output = input/divisor
Position Tracker: Rotary encoder generates UP/DOWN pulses; 74193 tracks absolute position (0-15); overflow/underflow via CO/BO
Address Generator: D0-D3 = start address; LOAD presets; UP/DOWN pulses scan memory addresses; read/write sequential locations

Alternative Models:What chips are recommended as replacements for SN74LS193N

الطراز	الشركة المصنعة	الفرق الرئيسي	الحزمة	Supply
74LS193N	TI/Nexperia	Original TTL version with 5V-only supply, typical propagation delay 10-15ns	DIP-16	5V TTL
74LS193D	TI/Nexperia	Surface-mount SOIC version of LS with identical logic function	SOIC-16	5V TTL
74HC193D	TI/Nexperia	CMOS version with wide 2-6V supply range, lower power consumption and higher noise immunity	SOIC-16	2-6V CMOS
74HC193N	TI/Nexperia	Through-hole DIP version of HC family for prototyping and repair	DIP-16	2-6V CMOS
74HCT193D	TI/Nexperia	CMOS with TTL-compatible input levels, ideal for mixing with LS devices at 5V	SOIC-16	4.5-5.5V TTL-in
74HCT193N	TI/Nexperia	Through-hole DIP version of HCT family for prototyping and repair	DIP-16	4.5-5.5V TTL-in

The 74193 is a 4-Bit Binary Counter (Up/Down). Family variants span from the original LS TTL (5V only) to modern LVC/AUP (down to 0.8V). HC and HCT versions offer 2-6V CMOS operation with HCT providing TTL-compatible input thresholds for mixed 5V systems. CD4000-series equivalents offer the widest 3-18V supply range at the cost of lower switching speed. DIP packages (N suffix) are through-hole; SOIC (D suffix) and TSSOP are surface-mount.