الصفحة الرئيسية > الدوائر المتكاملة الدوائر المتكاملة > CD4018BE

CD4018BE

5-stage Johnson counter, presettable divide-by-N (2-10), CMOS 3-18V, PDIP-16

2000

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جزء الشركة المصنعة ： جزء الشركة المصنعة

CD4018BE

الحزمة ： الحزمة

PDIP-16 (19.3 x 9.4 x 4.57mm, 2.54mm pitch, through-hole)

العلامة التجارية ： العلامة التجارية

فئات المنتجات:：فئات المنتجات

الدوائر المتكاملة الدوائر المتكاملة, واجهة ICs

توصيات أخرى قد تكون مهتماً بها.

SII9396SCNUC-BAR

IS43TR16256BL-125KBLI

الوصف

نظرة عامة على المنتج

The CD4018BE from Texas Instruments is a CMOS presettable divide-by-N counter using a 5-stage Johnson counter architecture — capable of dividing by any integer from 2 to 10 (or higher with cascading) in a 16-pin PDIP package.

المواصفات الرئيسية

الوظيفة	5-stage Johnson counter, presettable divide-by-N
Technology	CD4000B CMOS
جهد الإمداد	3V to 18V
Counter Stages	5 (Johnson/Johnson counter)
الحد الأقصى لتردد الساعة	10MHz typical @ VDD=10V
Trigger	Positive edge on CLK
إعادة تعيين	Asynchronous, active HIGH (RST)
Preset	5 individual JAM inputs + PRESET ENABLE (active HIGH)
Outputs	Q1, Q2, Q3, Q4, Q5 (buffered)
Data Input	DATA (serial, for feedback configuration)
درجة حرارة التشغيل	-55 درجة مئوية إلى +125 درجة مئوية
الحزمة	PDIP-16 (19.3 x 9.4mm)

الميزات

Johnson counter architecture — spike-free decoded outputs
Divide by 2, 3, 4, 5, 6, 7, 8, 9, or 10 with simple feedback
5 individual JAM inputs for presetting
Anti-lock gating ensures correct counting sequence
Schmitt trigger clock input
3V-18V wide supply range

التطبيقات

Programmable frequency dividers
Frequency synthesizers
Counter/timer control
Sequence generation

مقدمة المنتج:CD4018BE مقدمة المنتج

The CD4018BE from Texas Instruments is a 5-stage Johnson counter with preset capability, designed for programmable divide-by-N applications. Unlike binary ripple counters that divide only by powers of 2, the CD4018 can divide by any integer from 2 to 10 using simple feedback connections. The Johnson counter architecture produces spike-free outputs (unlike ripple counters) because only one bit changes per clock cycle. The divide ratio is set by feeding back one of the Q outputs (or its complement via a gate) to the DATA input: feed Q5̄ back for ÷10, Q4̄ for ÷8, Q3̄ for ÷6, Q2̄ for ÷4, Q1̄ for ÷2. For odd divisors (÷9, ÷7, ÷5, ÷3), a CD4011 gate combines two Q outputs before feeding back to DATA. The 5 JAM inputs (J1-J5) allow the counter to be preset to any Johnson state when PRESET ENABLE is HIGH, enabling programmable counters in frequency synthesizers. Multiple CD4018s can be cascaded for divisors greater than 10. The anti-lock gating ensures the counter always enters a valid Johnson sequence. The BE suffix denotes the PDIP-16 package.

مبدأ العمل:CD4018BE مبدأ العمل

The CD4018BE uses a 5-stage Johnson counter (also called twisted-ring counter). In a Johnson counter, the complement of the last stage is fed back to the first stage. Starting from all zeros: 00000→10000→11000→11100→11110→11111→01111→00111→00011→00001→00000. This 10-state cycle naturally divides by 10. The DATA input replaces the feedback when externally connected. For ÷10: Q5̄ → DATA (10 states). For ÷8: Q4̄ → DATA (8 states). For ÷6: Q3̄ → DATA. For ÷4: Q2̄ → DATA. For ÷2: Q1̄ → DATA. For odd divisors, a gate is needed: ÷9 uses Q5̄ AND Q1, ÷7 uses Q4̄ AND Q1, ÷5 uses Q3̄ AND Q1, ÷3 uses Q2̄ AND Q1. When PRESET ENABLE is HIGH, the JAM inputs (J1-J5) load directly into the counter stages on the next clock edge, overriding the DATA feedback. This allows starting the count at any state, enabling programmable division. The RESET input (RST=HIGH) clears all stages to 0. The anti-lock gating detects invalid states (Johnson counters can get stuck in unused states) and forces the counter into a valid sequence.

وصف الدبوس:CD4018BE تعريف الدبوس ووظائفه

دبوس	الاسم	النوع	الوصف
1	J5	المدخلات	Jam input for stage 5 (preset)
2	Q1	المخرجات	Stage 1 output
3	Q2	المخرجات	Stage 2 output
4	Q3	المخرجات	Stage 3 output
5	Q4	المخرجات	Stage 4 output
6	Q5	المخرجات	Stage 5 output
7	RST	المدخلات	Reset (active HIGH, clears all stages)
8	VSS	الطاقة	أرضي
9	CLK	المدخلات	Clock (positive edge triggered)
10	PE	المدخلات	Preset enable (active HIGH, loads J1-J5)
11	J1	المدخلات	Jam input for stage 1 (preset)
12	J2	المدخلات	Jam input for stage 2 (preset)
13	J3	المدخلات	Jam input for stage 3 (preset)
14	J4	المدخلات	Jam input for stage 4 (preset)
15	DATA	المدخلات	Serial data input (feedback for divide ratio)
16	VDD	الطاقة	Supply (3V to 18V)

Application Scenarios:In which products and applications isCD4018BE مستعمل

Divide-by-10: Q5 through inverter (or CD4069) → DATA; CLK input frequency; Q5 = CLK/10; no external gate needed if Q5̄ is available via inverter
Divide-by-7 (Odd): CD4011 NAND gate: Q4 AND Q1 → invert → DATA; produces 7-state cycle
Programmable Divider: Switch selects which Q output feeds back to DATA; 5-position switch = divide by 2,4,6,8,10
Frequency Synthesizer: Three CD4018s cascaded; each decade set via JAM inputs from thumbwheel switch; divide by 2-999

Alternative Models:What chips are recommended as replacements for CD4018BE

الطراز	الشركة المصنعة	الفرق الرئيسي	الحزمة	Supply
CD4018BM	TI	SOIC-16 surface-mount version with identical logic function and 3-18V range	SOIC-16	3-18V
CD4018BE	TI	Through-hole DIP version for prototyping and legacy board repair	DIP-16	3-18V
HEF4018BT	NXP	Pin-compatible CMOS version with improved ESD protection and 3-15V supply	SOIC-16	3-15V
MC144018BDR2G	أونسمي	Pin-compatible equivalent with RoHS compliance and AEC-Q100 automotive option	SOIC-16	3-18V
74HC190D	TI/Nexperia	HC CMOS version with higher speed and 2-6V supply for modern logic systems	SOIC-16	2-6V
74HC190N	TI/Nexperia	HC CMOS through-hole version for prototyping with 2-6V supply range	DIP-16	2-6V
74HCT190D	نيكسبيريا	HCT version with TTL-compatible inputs for mixed 5V TTL/CMOS systems	SOIC-16	4.5-5.5V

CD4018 is the CMOS 4000-series presettable divide-by-n counter operating over the wide 3-18V supply range. The HEF4018 (NXP) and MC144018 (onsemi) are direct pin-compatible equivalents. For higher speed at the cost of narrower voltage range, the 74HC190 HC/HCT families offer significantly faster propagation delay and lower power consumption at 2-6V. Surface-mount versions use the BM/M suffix (SOIC); through-hole versions use the BE suffix (DIP).