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74HC595D

8-bit shift register with latch, 3-state output, cascadable, SOIC-16, NXP 74HC595

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Manufacturer Part：

74HC595D

Package：

SOIC-16 (9.9 x 3.9 x 1.5mm)

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Description

Product Overview

The NXP 74HC595D is an 8-bit serial-in/parallel-out shift register with output latches and 3-state outputs in SOIC-16 package. Operating from 2.0V to 6.0V, it is widely used for expanding output ports on microcontrollers, driving LED arrays, and general-purpose serial-to-parallel data conversion.

Key Specifications

Logic Type 8-Bit Shift Register with Output Latch
Number of Bits 8
VCC Range 2.0V to 6.0V
Max Shift Frequency 54MHz at 6V
Output Drive ±7.8mA at 5V
Output Type 3-State
Package SOIC-16 (D)
Operating Temperature -40°C to +125°C

Features

  • 8-bit serial-in/parallel-out shift register
  • Separate output latch and 3-state control
  • Cascadable via serial output (Q7S)
  • 54MHz shift frequency at 6V
  • Asynchronous reset (MR)
  • SOIC-16 surface-mount package

Applications

  • LED matrix and display driving
  • MCU output port expansion
  • SPI-to-parallel data conversion
  • Seven-segment display multiplexing
  • Cascaded shift register chains

The NXP 74HC595D is an 8-bit serial-in/parallel-out shift register with output latches and 3-state outputs in SOIC-16 package. It is one of the most popular logic ICs for expanding MCU output capabilities, driving LED arrays, and implementing serial-to-parallel data conversion. Multiple devices can be cascaded using the serial output (Q7S) to create arbitrary-length shift register chains.

The 74HC595D has two 8-bit registers: a shift register and an output latch. Data is shifted into the shift register on each rising edge of the shift clock (SHCP). When the storage clock (STCP) rises, the shift register contents are transferred to the output latch. The 3-state output enable (OE) controls whether the latch outputs are active or high-impedance. The master reset (MR) asynchronously clears the shift register. The serial output (Q7S) provides the last bit of the shift register for cascading. This two-stage architecture allows new data to be shifted in while the outputs remain stable.

Pin Name Type Function
1 Q1 Output Parallel output bit 1
2 Q2 Output Parallel output bit 2
3 Q3 Output Parallel output bit 3
4 Q4 Output Parallel output bit 4
5 Q5 Output Parallel output bit 5
6 Q6 Output Parallel output bit 6
7 Q7 Output Parallel output bit 7
8 GND Power Ground
9 Q7S Output Serial output for cascading
10 MR Input Master reset (active low)
11 SHCP Input Shift register clock
12 STCP Input Storage register clock (latch)
13 OE Input Output enable (active low)
14 DS Input Serial data input
15 Q0 Output Parallel output bit 0
16 VCC Power Positive supply (2-6V)
  • LED matrix column/row driver via SPI
  • MCU GPIO expansion for relay/solenoid arrays
  • Seven-segment display digit multiplexing
  • Cascaded shift register chains for large LED installations
  • Serial-to-parallel address decoding
Manufacturer Part Number Package Notes
TI SN74HC595DR SOIC-16 Equivalent
onsemi MC74HC595DR2G SOIC-16 Equivalent
NXP 74HC595PW TSSOP-16 Smaller package
NXP 74HC595D-Q100 SOIC-16 Automotive qualified
NXP 74HCT595D SOIC-16 TTL-compatible inputs
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