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74HC138PW,118

3-to-8 Decoder/Demux, Inverting, 2-6V, 12ns, TSSOP-16

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Manufacturer Part：

74HC138PW,118

Package：

TSSOP-16 (5.0 x 4.4 x 1.1 mm)

Description

Product Overview

The 74HC138PW,118 from Nexperia is a 3-to-8 line decoder/demultiplexer with inverting outputs in a 16-pin TSSOP package, featuring three enable inputs for easy cascading.

Key Specifications

Type	3-to-8 Line Decoder/Demultiplexer
Logic Family	74HC (CMOS)
Supply Voltage	2.0 V to 6.0 V
Propagation Delay	12 ns (typical)
Output Drive	+/-5.2 mA
Enable Inputs	2 active LOW (E1, E2), 1 active HIGH (E3)
Outputs	8 active LOW (Y0-Y7)
Package	TSSOP-16
Operating Temperature	-40C to +125C

Features

3-to-8 line decoding with active LOW outputs
Three enable inputs for easy parallel expansion
Demultiplexing capability
Ideal for memory chip select decoding
ESD protection exceeds 2000 V HBM
Wide 2.0 V to 6.0 V supply range

Applications

Memory chip select decoding
I/O port address decoding
Data demultiplexing
Clock distribution networks

Product Introduction:74HC138PW,118 Product Introduction

The 74HC138PW,118 from Nexperia is a high-speed 3-to-8 line decoder/demultiplexer with inverting outputs. The device accepts three binary-weighted address inputs (A0, A1, A2) and, when enabled, provides eight mutually exclusive active LOW outputs (Y0 to Y7). Three enable inputs (two active LOW E1 and E2, one active HIGH E3) allow easy parallel expansion to a 1-of-32 decoder using four devices and one inverter. The 74HC138 can also function as an eight-output demultiplexer by using one enable input as the data input. The TSSOP-16 package provides a compact footprint for space-constrained designs.

Working Principle:74HC138PW,118 Working Principle

The 74HC138PW decodes a 3-bit binary address to activate one of eight outputs. The three address inputs (A0, A1, A2) select which output Yn goes LOW. All outputs remain HIGH unless the device is enabled (E1=LOW, E2=LOW, E3=HIGH). When enabled, the selected output corresponding to the binary address goes LOW while all other outputs remain HIGH. This implements the 3-to-8 decoding function. For demultiplexer operation, the data signal is applied to one of the active-LOW enable inputs while the other enables are held at their active states. The data is then routed to the output selected by the address inputs. The multiple enable inputs facilitate cascading: four 74HC138 devices plus one inverter create a 5-to-32 decoder without additional logic.

Pin Description:74HC138PW,118 Pin Definition and Functions

Pin	Name	Type	Function
1	A0	Input	Address input LSB
2	A1	Input	Address input
3	A2	Input	Address input MSB
4	E1	Input	Enable 1 (active LOW)
5	E2	Input	Enable 2 (active LOW)
6	E3	Input	Enable 3 (active HIGH)
7,9,10,11,12,13,14,15	Y7-Y0	Output	Decoded outputs (active LOW)
8	GND	Ground	Ground
16	VCC	Power	Supply voltage (2.0-6.0V)

Application Scenarios:In which products and applications is74HC138PW,118 used

Memory bank chip select decoding in multi-bank SRAM systems
I/O port address decoding for 8 peripheral devices
Clock demultiplexing to distribute one clock to 8 targets
1-of-32 decoder expansion using four cascaded devices

Alternative Models:What chips are recommended as replacements for 74HC138PW,118

Manufacturer	Part Number	Package	Notes
Nexperia	74HCT138PW	TSSOP-16	TTL input levels
TI	SN74HC138PWR	TSSOP-16	Pin-compatible
onsemi	MC74HC138ADTR2G	TSSOP-16	Pin-compatible
Nexperia	74HC138D	SOIC-16	Same function, wider package
Nexperia	74HC238PW	TSSOP-16	Non-inverting outputs