The EPM240F100C5N is a CPLD (Complex Programmable Logic Device) from Intel (formerly Altera) in TQFP-100 with 240 logic elements (LEs), 80 user I/O pins, and 80 macrocells. Each LE contains a 4-input look-up table (LUT), a programmable register (D/T/JK/SR flip-flop), and carry/interconnect logic. The MAX II architecture uses a Flash-based configuration storage that loads the device configuration in less than 100us on power-up, eliminating external configuration memory. The 240 LEs can implement approximately 240 equivalent macrocell functions, sufficient for glue logic, bus interfacing, I/O expansion, and simple state machines. The -F suffix denotes multi-voltage I/O support: 1.5V, 1.8V, 2.5V, or 3.3V I/O banks (4 independent banks). The -C5 speed grade provides 4.5ns pin-to-pin delay. The built-in JTAG interface supports in-system programming (ISP) and boundary-scan testing. The UFM (User Flash Memory) block provides 8192 bits of non-volatile storage for constants or configuration data. Typical power consumption is under 25mA static, making MAX II suitable for power-sensitive applications.