The XCF16PFSG48C is an AMD\/Xilinx Platform Flash in-system programmable configuration PROM with 16Mbit capacity, 1.8V supply, serial\/parallel config modes, design revisioning, and data decompression. Packaged in 48-CSPBGA, -40C to +85C.<\/p>\n
| Capacity<\/td>\n | 16 Mbit (2 MB)<\/td>\n<\/tr>\n | ||||||||||||||||||||||||||||||||||||
| Supply<\/td>\n | 1.8V<\/td>\n<\/tr>\n | ||||||||||||||||||||||||||||||||||||
| Config Modes<\/td>\n | Serial, SelectMAP (parallel)<\/td>\n<\/tr>\n | ||||||||||||||||||||||||||||||||||||
| Max Clock<\/td>\n | 33 MHz<\/td>\n<\/tr>\n | ||||||||||||||||||||||||||||||||||||
| Endurance<\/td>\n | 20,000 cycles<\/td>\n<\/tr>\n | ||||||||||||||||||||||||||||||||||||
| \u5305\u88c5<\/td>\n | 48-CSPBGA (8x9mm)<\/td>\n<\/tr>\n<\/table>\n\u7279\u70b9<\/h2>\n\u5e94\u7528<\/h2>\nProduct Overview The XCF16PFSG48C is an AMD\/Xilinx Platform Flash in-system programmable configuration PROM with 16Mbit capacity, 1.8V supply, serial\/parallel config modes, design revisioning, and data decompression. Packaged in 48-CSPBGA, -40C to +85C. Key Specifications Capacity 16 Mbit (2 MB) Supply 1.8V Config Modes Serial, SelectMAP (parallel) Max Clock 33 MHz Endurance 20,000 cycles Package 48-CSPBGA […]<\/p>\n","protected":false},"author":2,"featured_media":0,"comment_status":"open","ping_status":"","sticky":false,"template":"","format":"standard","meta":{"_acf_changed":false,"footnotes":""},"categories":[21,13],"tags":[594],"chip_brand":[175],"class_list":["post-8965","post","type-post","status-publish","format-standard","hentry","category-audio-ics","category-integrated-circuits-ics","tag-xcf16pfsg48c","chip_brand-xilinx"],"acf":{"brief_explanation":"Platform Flash PROM, 16Mbit, 1.8V, Serial\/SelectMAP, 48-CSPBGA","date_code":"","package_case":"48-CSPBGA (8 x 9 x 1.0 mm)","in_stock":180,"datasheet":"https:\/\/docs.amd.com\/r\/en-US\/pg123-platform-flash","price":"$8.50 @ 1+","product_introduction":"The XCF16PFSG48C is an AMD (formerly Xilinx) Platform Flash in-system programmable configuration PROM in a 48-pin CSPBGA package. The 16Mbit (2MByte) capacity stores configuration bitstreams for Xilinx FPGAs including Spartan-3, Spartan-6, and early Virtex families. The 1.8V supply (VCCINT) with VCCJ I\/O compatibility from 1.8V to 3.3V allows the PROM to interface with both 1.8V and 3.3V FPGA configuration pins. The device supports Master Serial, Slave Serial, Master SelectMAP, and Slave SelectMAP configuration modes, with the SelectMAP parallel interface reducing configuration time by bursting data 8 bits at a time. The design revisioning technology allows storing multiple FPGA design revisions and selecting between them at power-up via REVSEL pins, enabling A\/B firmware images for field upgrade with rollback. The built-in data decompressor is compatible with Xilinx BitGen compression, allowing larger compressed bitstreams to fit in the 16Mbit capacity. The C suffix indicates commercial temperature range (-40C to +85C). Note: This part is obsolete; use XCF16PVOG48C as replacement.","working_principle":"The XCF16PFSG48C uses a NOR Flash memory array organized as 16Mbit for storing FPGA configuration data. In Master Serial mode, the PROM outputs serial data on the DIN pin at up to 33MHz using an internal oscillator. In Slave Serial mode, the FPGA provides the CCLK that clocks data out. In SelectMAP mode, 8-bit parallel data is output on D0-D7 pins, reducing configuration time by approximately 8x. The JTAG TAP controller provides serial access for programming the Flash array via IEEE 1532. The address counter auto-increments during read for streaming the bitstream. The design revisioning uses the REVSEL[1:0] pins to select which stored design revision is accessed at configuration. The decompressor hardware inflates compressed bitstream data on-the-fly during configuration, transparent to the FPGA.","pin_description":"
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