The CS5532-BSZ is a Cirrus Logic 24-bit delta-sigma ADC with ultra-low-noise programmable gain instrumentation amplifier (PGIA). It features 2-channel differential input, gains of 1x to 64x, 6 nV\/sqrt(Hz) noise at 0.1 Hz, and 20 selectable output word rates from 6.25 to 3840 SPS. The device is packaged in a 20-pin SSOP rated for -40C to +85C.<\/p>\n
| Resolution<\/td>\n | 24 bits<\/td>\n<\/tr>\n | |||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||
| \u6e20\u9053<\/td>\n | 2 differential<\/td>\n<\/tr>\n | |||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||
| PGIA Gains<\/td>\n | 1x, 2x, 4x, 8x, 16x, 32x, 64x<\/td>\n<\/tr>\n | |||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||
| Input Noise<\/td>\n | 6 nV\/sqrt(Hz) at 0.1 Hz<\/td>\n<\/tr>\n | |||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||
| Linearity<\/td>\n | 0.0007% FS<\/td>\n<\/tr>\n | |||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||
| Word Rates<\/td>\n | 6.25 to 3840 SPS<\/td>\n<\/tr>\n<\/table>\n\u7279\u70b9<\/h2>\n\u5e94\u7528<\/h2>\nProduct Overview The CS5532-BSZ is a Cirrus Logic 24-bit delta-sigma ADC with ultra-low-noise programmable gain instrumentation amplifier (PGIA). It features 2-channel differential input, gains of 1x to 64x, 6 nV\/sqrt(Hz) noise at 0.1 Hz, and 20 selectable output word rates from 6.25 to 3840 SPS. The device is packaged in a 20-pin SSOP rated for […]<\/p>\n","protected":false},"author":2,"featured_media":0,"comment_status":"open","ping_status":"","sticky":false,"template":"","format":"standard","meta":{"_acf_changed":false,"footnotes":""},"categories":[19,13],"tags":[],"chip_brand":[165],"class_list":["post-8738","post","type-post","status-publish","format-standard","hentry","category-analog-linear-ics","category-integrated-circuits-ics","chip_brand-adi"],"acf":{"brief_explanation":"24-bit delta-sigma ADC, 2-ch, chopper-stabilized, 4800SPS, SSOP-20","date_code":"","package_case":"20-SSOP (5.30 x 7.20 mm)","in_stock":2500,"datasheet":"https:\/\/www.cirrus.com\/products\/cs5531-32\/","price":"$5.80 @ 1ku","product_introduction":"The Cirrus Logic CS5532-BSZ is a 24-bit delta-sigma analog-to-digital converter with two differential input channels and chopper-stabilized input amplifier, delivering 24-bit noise-free resolution at data rates up to 4800 SPS. The chopper-stabilized amplifier architecture virtually eliminates 1\/f (flicker) noise and input offset drift\u2014critical for weigh scale and strain gauge applications where DC accuracy over temperature is paramount. The input multiplexer supports two differential channels with on-chip cross-point multiplexing, allowing simultaneous measurement of multiple bridge circuits. The programmable gain amplifier (PGA) offers gains of 1x, 2x, 4x, 8x, 16x, 32x, and 64x, enabling direct connection of load cell outputs (typically 2 mV\/V) without external instrumentation amplifiers. At gain 64x, the input-referred noise is 8.8 nV\/sqrt(Hz), allowing resolution of microvolt-level signals. The SPI-compatible serial interface supports daisy-chain connection of multiple CS5532 devices on a single SPI bus, reducing wiring complexity in multi-channel systems. The device includes on-chip calibration registers for system-level offset and gain correction, compensating for external circuit tolerances. Power consumption is 35 mW from +\/-5V supplies, with a power-down mode reducing consumption to 5 mW.","working_principle":"The CS5532 uses a 4th-order delta-sigma modulator operating at an oversampled clock rate (MCLK = 4.9152 MHz typical). The modulator converts the analog input into a 1-bit data stream at the modulator frequency, and a digital decimation filter reduces the output rate to the user-selected data rate (3.84 to 4800 SPS in 15 steps) while increasing the effective resolution. The chopper-stabilized input amplifier eliminates 1\/f noise and offset drift by periodically swapping the amplifier input polarity and averaging the results\u2014any DC offset appears as a common-mode signal and is canceled in the averaging process. This chopping occurs at a rate well above the signal bandwidth, ensuring that the chopping artifacts are outside the passband of the digital filter. The PGA amplifies the differential input signal before the modulator, with gain accuracy of +\/-0.5% across all gain settings. System-level calibration is performed by applying known reference signals to the inputs and storing the correction coefficients in on-chip calibration registers. The self-calibration mode performs a quick offset and gain calibration using internal reference connections, while system calibration uses external reference signals for end-to-end calibration that includes external circuit errors.","pin_description":"
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