The DP83848IVVX is a 10\/100Mbps Ethernet physical layer transceiver (PHY) from Texas Instruments supporting MII\/RMII\/SNI interfaces with built-in Auto-MDIX, IEEE 802.3u compliant, in an LQFP-48 package, widely used in embedded Ethernet applications.<\/p>\n
DP83848IVVX Overview The DP83848IVVX is a 10\/100Mbps Ethernet physical layer transceiver (PHY) from Texas Instruments supporting MII\/RMII\/SNI interfaces with built-in Auto-MDIX, IEEE 802.3u compliant, in an LQFP-48 package, widely used in embedded Ethernet applications. Key Features Speed: 10\/100Mbps Interface: MII\/RMII\/SNI Supply voltage: 3.3V Auto-MDIX IEEE 802.3u compliant Built-in JTAG interface<\/p>","protected":false},"author":2,"featured_media":0,"comment_status":"open","ping_status":"","sticky":false,"template":"","format":"standard","meta":{"_acf_changed":false,"footnotes":""},"categories":[13,20],"tags":[],"chip_brand":[138],"class_list":["post-8022","post","type-post","status-publish","format-standard","hentry","category-integrated-circuits-ics","category-interface-ics","chip_brand-ti"],"acf":{"brief_explanation":"10\/100 Ethernet PHY, MII\/RMII, LQFP-48","date_code":"","package_case":"LQFP-48 (7.0 x 7.0 x 1.40 mm)","in_stock":11508,"datasheet":"https:\/\/www.ti.com\/lit\/ds\/symlink\/dp83848i.pdf","price":"$3.50 @ 1ku","product_introduction":"The DP83848IVVX is a single-port 10\/100 Mbps Ethernet physical layer (PHY) transceiver from Texas Instruments in a 48-pin LQFP (7 x 7 mm) package, designed for industrial temperature range (-40 C to +85 C). It implements the full IEEE 802.3 physical layer for 10BASE-T and 100BASE-TX Ethernet, featuring Auto-MDIX, MII\/RMII\/SNI MAC interfaces, IEEE 1149.1 JTAG boundary scan, 25 MHz clock output, and energy detection mode. Fabricated in 0.18 um CMOS at 3.3 V, it consumes less than 270 mW typical. The integrated adaptive equalizer and baseline wander compensation ensure error-free operation up to 150 meters of CAT5 cable.","working_principle":"The DP83848IVVX implements the complete Ethernet physical layer between the MAC (Media Access Controller) and the magnetics\/RJ45 connector. On the transmit path, the MAC transfers data to the PHY via the MII (4-bit nibble at 25 MHz for 100 Mbps or 2.5 MHz for 10 Mbps) or RMII (2-bit at 50 MHz) interface. The PHY encodes the data using 4B\/5B coding (100BASE-TX) or Manchester encoding (10BASE-T), scrambles it, and drives it through the internal MLT-3 (100 Mbps) or Manchester (10 Mbps) line encoder onto the differential transmit pair (TX+\/-) via the magnetics. On the receive path, the differential signal from the magnetics (RX+\/-) is amplified by the low-noise receiver, equalized by the adaptive equalizer (compensating for cable loss), decoded, and presented to the MAC via the MII\/RMII interface. Auto-negotiation automatically selects the highest common speed and duplex mode between the local and link partner. Auto-MDIX detects the cable type (straight or crossover) and internally swaps the TX and RX pairs as needed, eliminating crossover cable requirements. The 10\/100 Mbps Packet BIST (Built-In Self Test) enables manufacturing verification without external traffic generators.","pin_description":"
| Pin<\/th> | Name<\/th> | Description<\/th><\/tr> | ||||||||||||||||||||||||||||||||||||
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
| 1-4<\/td> | TXD[3:0]<\/td> | MII transmit data from MAC (4-bit nibble)<\/td><\/tr> | ||||||||||||||||||||||||||||||||||||
| 5<\/td> | TX_EN<\/td> | MII transmit enable<\/td><\/tr> | ||||||||||||||||||||||||||||||||||||
| 6<\/td> | TX_CLK<\/td> | MII transmit clock (25 MHz \/ 2.5 MHz)<\/td><\/tr> | ||||||||||||||||||||||||||||||||||||
| 7<\/td> | TX_ER<\/td> | MII transmit error indication<\/td><\/tr> | ||||||||||||||||||||||||||||||||||||
| 8-11<\/td> | RXD[3:0]<\/td> | MII receive data to MAC<\/td><\/tr> | ||||||||||||||||||||||||||||||||||||
| 12<\/td> | RX_DV<\/td> | MII receive data valid<\/td><\/tr> | ||||||||||||||||||||||||||||||||||||
| 13<\/td> | RX_CLK<\/td> | MII receive clock<\/td><\/tr> | ||||||||||||||||||||||||||||||||||||
| 14<\/td> | RX_ER<\/td> | MII receive error indication<\/td><\/tr> | ||||||||||||||||||||||||||||||||||||
| 15<\/td> | CRS<\/td> | Carrier sense; active during receive or transmit<\/td><\/tr> | ||||||||||||||||||||||||||||||||||||
| 16<\/td> | COL<\/td> | Collision detect; active during simultaneous TX\/RX<\/td><\/tr> | ||||||||||||||||||||||||||||||||||||
| 17<\/td> | MDC<\/td> | Management data clock (up to 25 MHz from MAC)<\/td><\/tr> | ||||||||||||||||||||||||||||||||||||
| 18<\/td> | MDIO<\/td> | Management data I\/O; bidirectional serial<\/td><\/tr> | ||||||||||||||||||||||||||||||||||||
| 19<\/td> | INTR<\/td> | Interrupt output; active low, programmable mask<\/td><\/tr> | ||||||||||||||||||||||||||||||||||||
| 20-22<\/td> | LED[2:0]<\/td> | Programmable LED outputs (link, speed, activity)<\/td><\/tr> | ||||||||||||||||||||||||||||||||||||
| 23<\/td> | X1<\/td> | 25 MHz crystal oscillator input or external clock<\/td><\/tr> | ||||||||||||||||||||||||||||||||||||
| 24<\/td> | X2<\/td> | Crystal oscillator output (leave NC with external clock)<\/td><\/tr> | ||||||||||||||||||||||||||||||||||||
| 25-26<\/td> | PMD-TX+\/PMD-TX-<\/td> | 100BASE-TX transmit pair to magnetics<\/td><\/tr> | ||||||||||||||||||||||||||||||||||||
| 27-28<\/td> | PMD-RX+\/PMD-RX-<\/td> | 100BASE-TX receive pair from magnetics<\/td><\/tr> | ||||||||||||||||||||||||||||||||||||
| 29-44<\/td> | VDD\/GND<\/td> | Power (3.3 V) and ground; multiple pins for clean supply<\/td><\/tr> | ||||||||||||||||||||||||||||||||||||
| 45<\/td> | JTAG_TCK<\/td> | JTAG test clock<\/td><\/tr> | ||||||||||||||||||||||||||||||||||||
| 46<\/td> | JTAG_TMS<\/td> | JTAG test mode select<\/td><\/tr> | ||||||||||||||||||||||||||||||||||||
| 47<\/td> | JTAG_TDI<\/td> | JTAG test data input<\/td><\/tr> | ||||||||||||||||||||||||||||||||||||
| 48<\/td> | JTAG_TDO<\/td> | JTAG test data output<\/td><\/tr><\/table>","application_scenarios":"
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