{"id":8012,"date":"2026-06-28T06:44:53","date_gmt":"2026-06-28T06:44:53","guid":{"rendered":"https:\/\/materialparts.com\/cd4019be\/"},"modified":"2026-06-28T11:43:56","modified_gmt":"2026-06-28T11:43:56","slug":"cd4019be","status":"publish","type":"post","link":"https:\/\/materialparts.com\/zh\/cd4019be\/","title":{"rendered":"CD4019BE"},"content":{"rendered":"<h2>\u4ea7\u54c1\u6982\u89c8<\/h2>\n<p>The CD4019BE from Texas Instruments is a quad AND-OR select gate that chooses between two 4-bit data sources under control of two select lines \u2014 a 4-channel 2:1 multiplexer built from AND-OR logic in a 16-pin PDIP package.<\/p>\n<h2>\u4e3b\u8981\u89c4\u683c<\/h2>\n<table>\n<tr>\n<td>\u529f\u80fd<\/td>\n<td>Quad AND-OR select gate (4-channel 2:1 multiplexer)<\/td>\n<\/tr>\n<tr>\n<td>Technology<\/td>\n<td>CD4000B CMOS<\/td>\n<\/tr>\n<tr>\n<td>\u7535\u6e90\u7535\u538b<\/td>\n<td>3V to 18V<\/td>\n<\/tr>\n<tr>\n<td>\u6e20\u9053<\/td>\n<td>4 (independent)<\/td>\n<\/tr>\n<tr>\n<td>Data Inputs<\/td>\n<td>A0,A1,A2,A3 and B0,B1,B2,B3<\/td>\n<\/tr>\n<tr>\n<td>Select Inputs<\/td>\n<td>KA (selects A group), KB (selects B group)<\/td>\n<\/tr>\n<tr>\n<td>\u4f20\u64ad\u5ef6\u8fdf<\/td>\n<td>150ns typical @ VDD=10V<\/td>\n<\/tr>\n<tr>\n<td>\u5de5\u4f5c\u6e29\u5ea6<\/td>\n<td>-55\u00b0C to +125\u00b0C<\/td>\n<\/tr>\n<tr>\n<td>\u5305\u88c5<\/td>\n<td>PDIP-16 (19.3 x 9.4mm)<\/td>\n<\/tr>\n<\/table>\n<h2>\u7279\u70b9<\/h2>\n<ul>\n<li>Four 2:1 multiplexer channels<\/li>\n<li>Two select inputs (KA, KB) for AND-OR selection<\/li>\n<li>Can select A only, B only, both, or neither<\/li>\n<li>3V-18V wide supply range<\/li>\n<\/ul>\n<h2>\u5e94\u7528<\/h2>\n<ul>\n<li>Data source selection<\/li>\n<li>AND-OR logic combination<\/li>\n<li>Parallel data switching<\/li>\n<li>Source multiplexing<\/li>\n<\/ul>","protected":false},"excerpt":{"rendered":"<p>Product Overview The CD4019BE from Texas Instruments is a quad AND-OR select gate that chooses between two 4-bit data sources under control of two select lines \u2014 a 4-channel 2:1 multiplexer built from AND-OR logic in a 16-pin PDIP package. Key Specifications Function Quad AND-OR select gate (4-channel 2:1 multiplexer) Technology CD4000B CMOS Supply Voltage [&hellip;]<\/p>\n","protected":false},"author":2,"featured_media":0,"comment_status":"open","ping_status":"","sticky":false,"template":"","format":"standard","meta":{"_acf_changed":false,"footnotes":""},"categories":[13,20],"tags":[],"chip_brand":[138],"class_list":["post-8012","post","type-post","status-publish","format-standard","hentry","category-integrated-circuits-ics","category-interface-ics","chip_brand-ti"],"acf":{"brief_explanation":"Quad AND-OR select gate, 4-channel 2:1 MUX, CMOS 3-18V, PDIP-16","date_code":"","package_case":"PDIP-16 (19.3 x 9.4 x 4.57mm, 2.54mm pitch, through-hole)","in_stock":2000,"datasheet":"https:\/\/www.ti.com\/lit\/ds\/symlink\/cd4019b.pdf","price":"$0.50 @ 1ku","product_introduction":"The CD4019BE from Texas Instruments is a quad AND-OR select gate that functions as a 4-channel 2:1 data multiplexer with a unique twist: two independent select inputs (KA and KB) allow four operating modes instead of the usual two. Each output Yi = (KA\u00b7Ai) + (KB\u00b7Bi). When KA=1 and KB=0: Yi = Ai (select source A). When KA=0 and KB=1: Yi = Bi (select source B). When KA=1 and KB=1: Yi = Ai + Bi (logical OR of both sources). When KA=0 and KB=0: Yi = 0 (all outputs forced LOW). The OR mode (both selects HIGH) is unique to the CD4019 \u2014 standard multiplexers don't provide this. It's useful for combining two data sources with OR logic, such as merging two sets of active-HIGH control lines. The CD4019 can also implement AND logic by using the complemented inputs. The BE suffix denotes the PDIP-16 package.","working_principle":"Each channel of the CD4019BE performs Yi = (KA \u00b7 Ai) + (KB \u00b7 Bi). The two AND gates per channel select which data input contributes to the output: KA gates the A input; KB gates the B input. The OR combines the selected inputs. Operating modes: (1) KA=1, KB=0: Yi=Ai (select A); (2) KA=0, KB=1: Yi=Bi (select B); (3) KA=1, KB=1: Yi=Ai+Bi (OR both sources); (4) KA=0, KB=0: Yi=0 (all outputs LOW, disabled). For standard 2:1 multiplexing: use KA and KB as complementary select signals (KA = SELECT, KB = NOT SELECT). When SELECT=1, A passes; when SELECT=0, B passes. For OR mode: tie KA and KB both HIGH; each output is the OR of the corresponding A and B inputs. For AND mode: use inverted data on B inputs; Yi = Ai\u00b7Bi\u0304 when KA=1, KB=1 (by DeMorgan's, the AND-OR becomes AND if B is inverted). The CD4019 is simpler than the CD4051 analog multiplexer (which passes analog signals) \u2014 the CD4019 is purely digital logic.","pin_description":"<table border=\"1\" cellpadding=\"4\">\n<tr><th>Pin<\/th><th>Name<\/th><th>Type<\/th><th>Description<\/th><\/tr>\n<tr><td>1<\/td><td>KB<\/td><td>Input<\/td><td>Select B (gates B0-B3 to outputs when HIGH)<\/td><\/tr>\n<tr><td>2<\/td><td>A3<\/td><td>Input<\/td><td>Channel 3 data input A<\/td><\/tr>\n<tr><td>3<\/td><td>B3<\/td><td>Input<\/td><td>Channel 3 data input B<\/td><\/tr>\n<tr><td>4<\/td><td>Y3<\/td><td>Output<\/td><td>Channel 3 output (KA\u00b7A3 + KB\u00b7B3)<\/td><\/tr>\n<tr><td>5<\/td><td>A2<\/td><td>Input<\/td><td>Channel 2 data input A<\/td><\/tr>\n<tr><td>6<\/td><td>B2<\/td><td>Input<\/td><td>Channel 2 data input B<\/td><\/tr>\n<tr><td>7<\/td><td>Y2<\/td><td>Output<\/td><td>Channel 2 output (KA\u00b7A2 + KB\u00b7B2)<\/td><\/tr>\n<tr><td>8<\/td><td>VSS<\/td><td>Power<\/td><td>Ground<\/td><\/tr>\n<tr><td>9<\/td><td>Y1<\/td><td>Output<\/td><td>Channel 1 output (KA\u00b7A1 + KB\u00b7B1)<\/td><\/tr>\n<tr><td>10<\/td><td>B1<\/td><td>Input<\/td><td>Channel 1 data input B<\/td><\/tr>\n<tr><td>11<\/td><td>A1<\/td><td>Input<\/td><td>Channel 1 data input A<\/td><\/tr>\n<tr><td>12<\/td><td>Y0<\/td><td>Output<\/td><td>Channel 0 output (KA\u00b7A0 + KB\u00b7B0)<\/td><\/tr>\n<tr><td>13<\/td><td>B0<\/td><td>Input<\/td><td>Channel 0 data input B<\/td><\/tr>\n<tr><td>14<\/td><td>A0<\/td><td>Input<\/td><td>Channel 0 data input A<\/td><\/tr>\n<tr><td>15<\/td><td>KA<\/td><td>Input<\/td><td>Select A (gates A0-A3 to outputs when HIGH)<\/td><\/tr>\n<tr><td>16<\/td><td>VDD<\/td><td>Power<\/td><td>Supply (3V to 18V)<\/td><\/tr>\n<\/table>","application_scenarios":"<ul>\n<li><strong>2:1 Data MUX:<\/strong> Source A \u2192 A0-A3; Source B \u2192 B0-B3; SELECT \u2192 KA; NOT SELECT \u2192 KB; Y0-Y3 = selected 4-bit source<\/li>\n<li><strong>OR Combiner:<\/strong> KA=KB=1; Yi = Ai+Bi; merge two sets of active-HIGH control signals; any active input drives output<\/li>\n<li><strong>Gated Data:<\/strong> KA = enable; KB = 0; Yi = enable\u00b7Ai; data passes only when enable is HIGH; forced LOW when disabled<\/li>\n<li><strong>Parallel Switch:<\/strong> Two 4-bit registers \u2192 A0-A3 and B0-B3; KA\/KB select which register drives the bus; register file output select<\/li>\n<\/ul>","alternative_models":"<table border=\"1\" cellpadding=\"4\">\n<tr><th>Model<\/th><th>Manufacturer<\/th><th>Key Difference<\/th><th>Package<\/th><th>Supply<\/th><\/tr>\n<tr><td>CD4019BM<\/td><td>TI<\/td><td>SOIC-16 surface-mount version with identical logic function and 3-18V range<\/td><td>SOIC-16<\/td><td>3-18V<\/td><\/tr>\n<tr><td>CD4019BE<\/td><td>TI<\/td><td>Through-hole DIP version for prototyping and legacy board repair<\/td><td>DIP-16<\/td><td>3-18V<\/td><\/tr>\n<tr><td>HEF4019BT<\/td><td>NXP<\/td><td>Pin-compatible CMOS version with improved ESD protection and 3-15V supply<\/td><td>SOIC-16<\/td><td>3-15V<\/td><\/tr>\n<tr><td>MC144019BDR2G<\/td><td>onsemi<\/td><td>Pin-compatible equivalent with RoHS compliance and AEC-Q100 automotive option<\/td><td>SOIC-16<\/td><td>3-18V<\/td><\/tr>\n<tr><td>74HC157D<\/td><td>TI\/Nexperia<\/td><td>HC CMOS version with higher speed and 2-6V supply for modern logic systems<\/td><td>SOIC-16<\/td><td>2-6V<\/td><\/tr>\n<tr><td>74HC157N<\/td><td>TI\/Nexperia<\/td><td>HC CMOS through-hole version for prototyping with 2-6V supply range<\/td><td>DIP-16<\/td><td>2-6V<\/td><\/tr>\n<tr><td>74HCT157D<\/td><td>Nexperia<\/td><td>HCT version with TTL-compatible inputs for mixed 5V TTL\/CMOS systems<\/td><td>SOIC-16<\/td><td>4.5-5.5V<\/td><\/tr>\n<\/table>\n<p>CD4019 is the CMOS 4000-series quad 2:1 multiplexer operating over the wide 3-18V supply range. The HEF4019 (NXP) and MC144019 (onsemi) are direct pin-compatible equivalents. For higher speed at the cost of narrower voltage range, the 74HC157 HC\/HCT families offer significantly faster propagation delay and lower power consumption at 2-6V. Surface-mount versions use the BM\/M suffix (SOIC); through-hole versions use the BE suffix (DIP).<\/p>"},"_links":{"self":[{"href":"https:\/\/materialparts.com\/zh\/wp-json\/wp\/v2\/posts\/8012","targetHints":{"allow":["GET"]}}],"collection":[{"href":"https:\/\/materialparts.com\/zh\/wp-json\/wp\/v2\/posts"}],"about":[{"href":"https:\/\/materialparts.com\/zh\/wp-json\/wp\/v2\/types\/post"}],"author":[{"embeddable":true,"href":"https:\/\/materialparts.com\/zh\/wp-json\/wp\/v2\/users\/2"}],"replies":[{"embeddable":true,"href":"https:\/\/materialparts.com\/zh\/wp-json\/wp\/v2\/comments?post=8012"}],"version-history":[{"count":1,"href":"https:\/\/materialparts.com\/zh\/wp-json\/wp\/v2\/posts\/8012\/revisions"}],"predecessor-version":[{"id":8127,"href":"https:\/\/materialparts.com\/zh\/wp-json\/wp\/v2\/posts\/8012\/revisions\/8127"}],"wp:attachment":[{"href":"https:\/\/materialparts.com\/zh\/wp-json\/wp\/v2\/media?parent=8012"}],"wp:term":[{"taxonomy":"category","embeddable":true,"href":"https:\/\/materialparts.com\/zh\/wp-json\/wp\/v2\/categories?post=8012"},{"taxonomy":"post_tag","embeddable":true,"href":"https:\/\/materialparts.com\/zh\/wp-json\/wp\/v2\/tags?post=8012"},{"taxonomy":"chip_brand","embeddable":true,"href":"https:\/\/materialparts.com\/zh\/wp-json\/wp\/v2\/chip_brand?post=8012"}],"curies":[{"name":"wp","href":"https:\/\/api.w.org\/{rel}","templated":true}]}}