{"id":8011,"date":"2026-06-28T06:44:51","date_gmt":"2026-06-28T06:44:51","guid":{"rendered":"https:\/\/materialparts.com\/sn74ls193n-2\/"},"modified":"2026-06-28T11:43:58","modified_gmt":"2026-06-28T11:43:58","slug":"sn74ls193n-2","status":"publish","type":"post","link":"https:\/\/materialparts.com\/zh\/sn74ls193n-2\/","title":{"rendered":"SN74LS193N"},"content":{"rendered":"

\u4ea7\u54c1\u6982\u89c8<\/h2>\n

The SN74LS193N from Texas Instruments is a synchronous 4-bit binary up\/down counter with separate clocks, parallel load, and clear \u2014 the binary (0-15) version of the 74192 in a 16-pin PDIP package.<\/p>\n

\u4e3b\u8981\u89c4\u683c<\/h2>\n\n\n\n\n\n\n\n\n\n\n\n\n
\u529f\u80fd<\/td>\nSynchronous 4-bit binary up\/down counter<\/td>\n<\/tr>\n
\u903b\u8f91\u5bb6\u65cf<\/td>\nLS (Low-power Schottky)<\/td>\n<\/tr>\n
\u7535\u6e90\u7535\u538b<\/td>\n4.75V to 5.25V<\/td>\n<\/tr>\n
Count Range<\/td>\n0-15 (4-bit binary)<\/td>\n<\/tr>\n
Clock Inputs<\/td>\nUP (count up), DOWN (count down), separate, negative-edge<\/td>\n<\/tr>\n
Parallel Load<\/td>\nAsynchronous, active-LOW (LOAD)<\/td>\n<\/tr>\n
Clear<\/td>\nAsynchronous, active-HIGH (CLR)<\/td>\n<\/tr>\n
Carry\/Borrow<\/td>\nCO (carry, active-LOW), BO (borrow, active-LOW)<\/td>\n<\/tr>\n
Max Clock Frequency<\/td>\n25MHz typical<\/td>\n<\/tr>\n
\u5de5\u4f5c\u6e29\u5ea6<\/td>\n0\u00b0C to +70\u00b0C<\/td>\n<\/tr>\n
\u5305\u88c5<\/td>\nPDIP-16 (19.3 x 6.35mm)<\/td>\n<\/tr>\n<\/table>\n

\u7279\u70b9<\/h2>\n
    \n
  • Separate UP and DOWN clock inputs<\/li>\n
  • Binary count: 0-15 up, 15-0 down<\/li>\n
  • Asynchronous parallel load and clear<\/li>\n
  • Carry\/borrow outputs for cascading<\/li>\n
  • Same pinout as SN74LS192N<\/li>\n<\/ul>\n

    \u5e94\u7528<\/h2>\n
      \n
    • Binary up\/down counters<\/li>\n
    • Address generation<\/li>\n
    • Programmable frequency dividers<\/li>\n
    • Digital position tracking<\/li>\n<\/ul>","protected":false},"excerpt":{"rendered":"

      Product Overview The SN74LS193N from Texas Instruments is a synchronous 4-bit binary up\/down counter with separate clocks, parallel load, and clear \u2014 the binary (0-15) version of the 74192 in a 16-pin PDIP package. Key Specifications Function Synchronous 4-bit binary up\/down counter Logic Family LS (Low-power Schottky) Supply Voltage 4.75V to 5.25V Count Range 0-15 […]<\/p>\n","protected":false},"author":2,"featured_media":0,"comment_status":"open","ping_status":"","sticky":false,"template":"","format":"standard","meta":{"_acf_changed":false,"footnotes":""},"categories":[13,20],"tags":[],"chip_brand":[138],"class_list":["post-8011","post","type-post","status-publish","format-standard","hentry","category-integrated-circuits-ics","category-interface-ics","chip_brand-ti"],"acf":{"brief_explanation":"4-bit binary up\/down counter, separate clocks, async load\/clear, carry\/borrow, LS TTL, PDIP-16","date_code":"","package_case":"PDIP-16 (19.3 x 6.35 x 4.57mm, 2.54mm pitch, through-hole)","in_stock":3000,"datasheet":"https:\/\/www.ti.com\/lit\/ds\/symlink\/sn74ls193.pdf","price":"$1.00 @ 1ku","product_introduction":"The SN74LS193N from Texas Instruments is a synchronous 4-bit binary up\/down counter with the same architecture as the 74192 but counting in binary (0-15) instead of BCD (0-9). It features separate UP and DOWN clock inputs, asynchronous parallel load, asynchronous clear, and carry\/borrow outputs. The dual-clock design means counting direction is determined by which clock receives pulses: UP counts 0\u21921\u2192...\u219215\u21920; DOWN counts 15\u219214\u2192...\u21920\u219215. The carry output (CO) goes LOW when the count is 15 and an UP pulse arrives; the borrow output (BO) goes LOW when the count is 0 and a DOWN pulse arrives. These outputs cascade directly to the next stage's UP\/DOWN inputs for multi-stage counters. The 74193 is identical to the 74192 in pinout and functionality \u2014 the only difference is the count modulus (16 vs 10). The 74193 is preferred when the full 0-15 range is needed, such as in address generation, binary frequency division, and digital signal processing. The N suffix denotes the PDIP-16 package.","working_principle":"The SN74LS193N counts in binary (0-15) on the negative edge of the UP or DOWN clock. Counting UP: pulses on UP, DOWN must be HIGH. Sequence: 0\u21921\u21922\u2192...\u219215\u21920 (carry). At 15, CO goes LOW on the next UP clock. Counting DOWN: pulses on DOWN, UP must be HIGH. Sequence: 15\u219214\u2192...\u21921\u21920\u219215 (borrow). At 0, BO goes LOW on the next DOWN clock. Parallel load: LOAD=LOW loads D0-D3 into the counter asynchronously. CLR=HIGH resets to 0 asynchronously. Priority: CLR > LOAD > clocks. For multi-stage cascading: CO of stage 1 \u2192 UP of stage 2; BO of stage 1 \u2192 DOWN of stage 2. Two stages count 0-255 (8-bit); four stages count 0-65535 (16-bit). The separate UP\/DOWN clocks allow independent control of increment and decrement \u2014 useful when UP and DOWN signals come from different sources (e.g., two rotary encoders, or increment\/decrement buttons).","pin_description":"\n
      Pin<\/th>Name<\/th>Type<\/th>Description<\/th><\/tr>\n
      1<\/td>DOWN<\/td>Input<\/td>Count-down clock (negative edge, UP must be HIGH)<\/td><\/tr>\n
      2<\/td>Q1<\/td>Output<\/td>Output bit 1<\/td><\/tr>\n
      3<\/td>Q0<\/td>Output<\/td>Output bit 0 (LSB)<\/td><\/tr>\n
      4<\/td>BO<\/td>Output<\/td>Borrow output (active-LOW; LOW at count=0 with DOWN clock)<\/td><\/tr>\n
      5<\/td>CO<\/td>Output<\/td>Carry output (active-LOW; LOW at count=15 with UP clock)<\/td><\/tr>\n
      6<\/td>Q3<\/td>Output<\/td>Output bit 3 (MSB)<\/td><\/tr>\n
      7<\/td>Q2<\/td>Output<\/td>Output bit 2<\/td><\/tr>\n
      8<\/td>GND<\/td>Power<\/td>Ground<\/td><\/tr>\n
      9<\/td>D2<\/td>Input<\/td>Parallel data input bit 2<\/td><\/tr>\n
      10<\/td>D3<\/td>Input<\/td>Parallel data input bit 3 (MSB)<\/td><\/tr>\n
      11<\/td>D0<\/td>Input<\/td>Parallel data input bit 0 (LSB)<\/td><\/tr>\n
      12<\/td>D1<\/td>Input<\/td>Parallel data input bit 1<\/td><\/tr>\n
      13<\/td>LOAD<\/td>Input<\/td>Parallel load enable (active-LOW, loads D0-D3)<\/td><\/tr>\n
      14<\/td>CLR<\/td>Input<\/td>Asynchronous clear (active-HIGH, resets to 0)<\/td><\/tr>\n
      15<\/td>UP<\/td>Input<\/td>Count-up clock (negative edge, DOWN must be HIGH)<\/td><\/tr>\n
      16<\/td>VCC<\/td>Power<\/td>Supply (5V)<\/td><\/tr>\n<\/table>","application_scenarios":"
        \n
      • 8-Bit Binary Counter:<\/strong> Two 74193s; CO(#1) \u2192 UP(#2); BO(#1) \u2192 DOWN(#2); 8-bit count 0-255; cascaded carry\/borrow<\/li>\n
      • Programmable Divider:<\/strong> Preset divisor-1 on D0-D3; LOAD presets counter; count down to 0; BO reloads preset; output = input\/divisor<\/li>\n
      • Position Tracker:<\/strong> Rotary encoder generates UP\/DOWN pulses; 74193 tracks absolute position (0-15); overflow\/underflow via CO\/BO<\/li>\n
      • Address Generator:<\/strong> D0-D3 = start address; LOAD presets; UP\/DOWN pulses scan memory addresses; read\/write sequential locations<\/li>\n<\/ul>","alternative_models":"\n
        Model<\/th>Manufacturer<\/th>Key Difference<\/th>Package<\/th>Supply<\/th><\/tr>\n
        74LS193N<\/td>TI\/Nexperia<\/td>Original TTL version with 5V-only supply, typical propagation delay 10-15ns<\/td>DIP-16<\/td>5V TTL<\/td><\/tr>\n
        74LS193D<\/td>TI\/Nexperia<\/td>Surface-mount SOIC version of LS with identical logic function<\/td>SOIC-16<\/td>5V TTL<\/td><\/tr>\n
        74HC193D<\/td>TI\/Nexperia<\/td>CMOS version with wide 2-6V supply range, lower power consumption and higher noise immunity<\/td>SOIC-16<\/td>2-6V CMOS<\/td><\/tr>\n
        74HC193N<\/td>TI\/Nexperia<\/td>Through-hole DIP version of HC family for prototyping and repair<\/td>DIP-16<\/td>2-6V CMOS<\/td><\/tr>\n
        74HCT193D<\/td>TI\/Nexperia<\/td>CMOS with TTL-compatible input levels, ideal for mixing with LS devices at 5V<\/td>SOIC-16<\/td>4.5-5.5V TTL-in<\/td><\/tr>\n
        74HCT193N<\/td>TI\/Nexperia<\/td>Through-hole DIP version of HCT family for prototyping and repair<\/td>DIP-16<\/td>4.5-5.5V TTL-in<\/td><\/tr>\n<\/table>\n

        The 74193 is a 4-Bit Binary Counter (Up\/Down). Family variants span from the original LS TTL (5V only) to modern LVC\/AUP (down to 0.8V). HC and HCT versions offer 2-6V CMOS operation with HCT providing TTL-compatible input thresholds for mixed 5V systems. CD4000-series equivalents offer the widest 3-18V supply range at the cost of lower switching speed. DIP packages (N suffix) are through-hole; SOIC (D suffix) and TSSOP are surface-mount.<\/p>"},"_links":{"self":[{"href":"https:\/\/materialparts.com\/zh\/wp-json\/wp\/v2\/posts\/8011","targetHints":{"allow":["GET"]}}],"collection":[{"href":"https:\/\/materialparts.com\/zh\/wp-json\/wp\/v2\/posts"}],"about":[{"href":"https:\/\/materialparts.com\/zh\/wp-json\/wp\/v2\/types\/post"}],"author":[{"embeddable":true,"href":"https:\/\/materialparts.com\/zh\/wp-json\/wp\/v2\/users\/2"}],"replies":[{"embeddable":true,"href":"https:\/\/materialparts.com\/zh\/wp-json\/wp\/v2\/comments?post=8011"}],"version-history":[{"count":1,"href":"https:\/\/materialparts.com\/zh\/wp-json\/wp\/v2\/posts\/8011\/revisions"}],"predecessor-version":[{"id":8128,"href":"https:\/\/materialparts.com\/zh\/wp-json\/wp\/v2\/posts\/8011\/revisions\/8128"}],"wp:attachment":[{"href":"https:\/\/materialparts.com\/zh\/wp-json\/wp\/v2\/media?parent=8011"}],"wp:term":[{"taxonomy":"category","embeddable":true,"href":"https:\/\/materialparts.com\/zh\/wp-json\/wp\/v2\/categories?post=8011"},{"taxonomy":"post_tag","embeddable":true,"href":"https:\/\/materialparts.com\/zh\/wp-json\/wp\/v2\/tags?post=8011"},{"taxonomy":"chip_brand","embeddable":true,"href":"https:\/\/materialparts.com\/zh\/wp-json\/wp\/v2\/chip_brand?post=8011"}],"curies":[{"name":"wp","href":"https:\/\/api.w.org\/{rel}","templated":true}]}}