{"id":8000,"date":"2026-06-28T06:38:12","date_gmt":"2026-06-28T06:38:12","guid":{"rendered":"https:\/\/materialparts.com\/sn74ls109n\/"},"modified":"2026-06-28T11:44:15","modified_gmt":"2026-06-28T11:44:15","slug":"sn74ls109n","status":"publish","type":"post","link":"https:\/\/materialparts.com\/zh\/sn74ls109n\/","title":{"rendered":"SN74LS109N"},"content":{"rendered":"

\u4ea7\u54c1\u6982\u89c8<\/h2>\n

The SN74LS109N from Texas Instruments contains two independent J-K positive-edge-triggered flip-flops with complementary outputs, preset and clear \u2014 the positive-edge version of the 7476 in a 16-pin PDIP package.<\/p>\n

\u4e3b\u8981\u89c4\u683c<\/h2>\n\n\n\n\n\n\n\n\n\n\n\n
Number of Flip-Flops<\/td>\n2 (dual, independent)<\/td>\n<\/tr>\n
\u903b\u8f91\u5bb6\u65cf<\/td>\nLS (Low-power Schottky)<\/td>\n<\/tr>\n
Trigger Type<\/td>\nPositive-edge (rising edge of CLK)<\/td>\n<\/tr>\n
\u7535\u6e90\u7535\u538b<\/td>\n4.75V to 5.25V<\/td>\n<\/tr>\n
Max Clock Frequency<\/td>\n25MHz typical<\/td>\n<\/tr>\n
Preset (PRE)<\/td>\nActive-LOW (asynchronous, sets Q=1)<\/td>\n<\/tr>\n
Clear (CLR)<\/td>\nActive-LOW (asynchronous, sets Q=0)<\/td>\n<\/tr>\n
\u4f20\u64ad\u5ef6\u8fdf<\/td>\n16ns typical (CLK to Q)<\/td>\n<\/tr>\n
\u5de5\u4f5c\u6e29\u5ea6<\/td>\n0\u00b0C to +70\u00b0C<\/td>\n<\/tr>\n
\u5305\u88c5<\/td>\nPDIP-16 (19.3 x 6.35mm)<\/td>\n<\/tr>\n<\/table>\n

\u7279\u70b9<\/h2>\n
    \n
  • Dual J-K positive-edge-triggered flip-flops<\/li>\n
  • Active-LOW preset and clear (asynchronous)<\/li>\n
  • Complementary outputs (Q and NOT-Q)<\/li>\n
  • Toggle mode: J=1,K=1<\/li>\n
  • Same pinout as SN74LS73N but with preset<\/li>\n<\/ul>\n

    \u5e94\u7528<\/h2>\n
      \n
    • Synchronous counters<\/li>\n
    • Toggle flip-flops \/ frequency dividers<\/li>\n
    • Control logic<\/li>\n
    • Data registers<\/li>\n<\/ul>","protected":false},"excerpt":{"rendered":"

      Product Overview The SN74LS109N from Texas Instruments contains two independent J-K positive-edge-triggered flip-flops with complementary outputs, preset and clear \u2014 the positive-edge version of the 7476 in a 16-pin PDIP package. Key Specifications Number of Flip-Flops 2 (dual, independent) Logic Family LS (Low-power Schottky) Trigger Type Positive-edge (rising edge of CLK) Supply Voltage 4.75V to […]<\/p>\n","protected":false},"author":2,"featured_media":0,"comment_status":"open","ping_status":"","sticky":false,"template":"","format":"standard","meta":{"_acf_changed":false,"footnotes":""},"categories":[13,20],"tags":[],"chip_brand":[138],"class_list":["post-8000","post","type-post","status-publish","format-standard","hentry","category-integrated-circuits-ics","category-interface-ics","chip_brand-ti"],"acf":{"brief_explanation":"Dual J-K flip-flop, positive-edge, preset\/clear, LS TTL, PDIP-16","date_code":"","package_case":"PDIP-16 (19.3 x 6.35 x 4.57mm, 2.54mm pitch, through-hole)","in_stock":3000,"datasheet":"https:\/\/www.ti.com\/lit\/ds\/symlink\/sn74ls109a.pdf","price":"$0.45 @ 1ku","product_introduction":"The SN74LS109N from Texas Instruments contains two independent J-K positive-edge-triggered flip-flops with direct preset (PRE, active-LOW) and clear (CLR, active-LOW). It combines the J-K functionality of the 7476 with the positive-edge triggering of the 7474 D flip-flop. On each rising clock edge, the Q output is updated based on the J and K inputs: J=0,K=0 \u2192 hold; J=1,K=0 \u2192 set (Q=1); J=0,K=1 \u2192 reset (Q=0); J=1,K=1 \u2192 toggle. The positive-edge triggering makes the 74109 compatible with synchronous counter designs where all flip-flops share a common clock and update simultaneously \u2014 unlike the 7476's negative-edge triggering which can cause ripple delays in synchronous systems. The active-LOW preset and clear override the clocked operation. The 74109 is the preferred J-K flip-flop for synchronous counter design because the positive-edge triggering aligns with the standard clock convention. The N suffix denotes the PDIP-16 through-hole package.","working_principle":"Each J-K flip-flop in the SN74LS109N captures the J and K input states on the rising edge of CLK and updates Q accordingly. Truth table (on rising CLK edge): J=0,K=0 \u2192 Q holds; J=1,K=0 \u2192 Q=1 (set); J=0,K=1 \u2192 Q=0 (reset); J=1,K=1 \u2192 Q toggles. The asynchronous inputs override: PRE=LOW forces Q=1; CLR=LOW forces Q=0. For normal operation, PRE and CLR must both be HIGH. The positive-edge triggering means all flip-flops in a synchronous system update at the same time when they share a common clock \u2014 critical for synchronous counter design where ripple delays would cause incorrect operation. For a synchronous 2-bit counter: both 74109 flip-flops share the same CLK; FF1 J=K=1 (always toggle); FF2 J=K=Q1 (toggle only when Q1=1); both update simultaneously on each clock edge, counting 00\u219201\u219210\u219211\u219200. This avoids the ripple delay of cascaded negative-edge counters (like 7476).","pin_description":"\n
      Pin<\/th>Name<\/th>Type<\/th>Description<\/th><\/tr>\n
      1<\/td>1CLR<\/td>Input<\/td>Flip-flop 1 clear (active LOW)<\/td><\/tr>\n
      2<\/td>1J<\/td>Input<\/td>Flip-flop 1 J input<\/td><\/tr>\n
      3<\/td>1K<\/td>Input<\/td>Flip-flop 1 K input (K\u0304 in some sources)<\/td><\/tr>\n
      4<\/td>1CLK<\/td>Input<\/td>Flip-flop 1 clock (positive edge)<\/td><\/tr>\n
      5<\/td>1PRE<\/td>Input<\/td>Flip-flop 1 preset (active LOW)<\/td><\/tr>\n
      6<\/td>1Q<\/td>Output<\/td>Flip-flop 1 Q output<\/td><\/tr>\n
      7<\/td>1NOT-Q<\/td>Output<\/td>Flip-flop 1 complementary output<\/td><\/tr>\n
      8<\/td>GND<\/td>Power<\/td>Ground<\/td><\/tr>\n
      9<\/td>2NOT-Q<\/td>Output<\/td>Flip-flop 2 complementary output<\/td><\/tr>\n
      10<\/td>2Q<\/td>Output<\/td>Flip-flop 2 Q output<\/td><\/tr>\n
      11<\/td>2PRE<\/td>Input<\/td>Flip-flop 2 preset (active LOW)<\/td><\/tr>\n
      12<\/td>2CLK<\/td>Input<\/td>Flip-flop 2 clock (positive edge)<\/td><\/tr>\n
      13<\/td>2K<\/td>Input<\/td>Flip-flop 2 K input<\/td><\/tr>\n
      14<\/td>2J<\/td>Input<\/td>Flip-flop 2 J input<\/td><\/tr>\n
      15<\/td>2CLR<\/td>Input<\/td>Flip-flop 2 clear (active LOW)<\/td><\/tr>\n
      16<\/td>VCC<\/td>Power<\/td>Supply (5V)<\/td><\/tr>\n<\/table>","application_scenarios":"
        \n
      • Synchronous 2-Bit Counter:<\/strong> Shared CLK; FF1: J=K=1; FF2: J=K=Q1; both update simultaneously; counts 00\u219201\u219210\u219211\u219200<\/li>\n
      • Toggle \/ \u00f72:<\/strong> J=K=1 (tied HIGH); clock on CLK; Q toggles each rising edge<\/li>\n
      • Controlled Toggle:<\/strong> J=enable, K=enable; enable=HIGH \u2192 toggle; enable=LOW \u2192 hold<\/li>\n
      • D Flip-Flop Substitute:<\/strong> J=data, K=NOT-data (via inverter); Q = data on rising CLK edge<\/li>\n<\/ul>","alternative_models":"\n
        Model<\/th>Manufacturer<\/th>Key Difference<\/th>Package<\/th>Supply<\/th><\/tr>\n
        74LS109N<\/td>TI\/Nexperia<\/td>Original TTL version with 5V-only supply, typical propagation delay 10-15ns<\/td>DIP-16<\/td>5V TTL<\/td><\/tr>\n
        74LS109D<\/td>TI\/Nexperia<\/td>Surface-mount SOIC version of LS with identical logic function<\/td>SOIC-16<\/td>5V TTL<\/td><\/tr>\n
        74HC109D<\/td>TI\/Nexperia<\/td>CMOS version with wide 2-6V supply range, lower power consumption and higher noise immunity<\/td>SOIC-16<\/td>2-6V CMOS<\/td><\/tr>\n
        74HC109N<\/td>TI\/Nexperia<\/td>Through-hole DIP version of HC family for prototyping and repair<\/td>DIP-16<\/td>2-6V CMOS<\/td><\/tr>\n
        74HCT109D<\/td>TI\/Nexperia<\/td>CMOS with TTL-compatible input levels, ideal for mixing with LS devices at 5V<\/td>SOIC-16<\/td>4.5-5.5V TTL-in<\/td><\/tr>\n
        74HCT109N<\/td>TI\/Nexperia<\/td>Through-hole DIP version of HCT family for prototyping and repair<\/td>DIP-16<\/td>4.5-5.5V TTL-in<\/td><\/tr>\n<\/table>\n

        The 74109 is a Dual J-K Positive-Edge-Triggered Flip-Flop. Family variants span from the original LS TTL (5V only) to modern LVC\/AUP (down to 0.8V). HC and HCT versions offer 2-6V CMOS operation with HCT providing TTL-compatible input thresholds for mixed 5V systems. CD4000-series equivalents offer the widest 3-18V supply range at the cost of lower switching speed. DIP packages (N suffix) are through-hole; SOIC (D suffix) and TSSOP are surface-mount.<\/p>"},"_links":{"self":[{"href":"https:\/\/materialparts.com\/zh\/wp-json\/wp\/v2\/posts\/8000","targetHints":{"allow":["GET"]}}],"collection":[{"href":"https:\/\/materialparts.com\/zh\/wp-json\/wp\/v2\/posts"}],"about":[{"href":"https:\/\/materialparts.com\/zh\/wp-json\/wp\/v2\/types\/post"}],"author":[{"embeddable":true,"href":"https:\/\/materialparts.com\/zh\/wp-json\/wp\/v2\/users\/2"}],"replies":[{"embeddable":true,"href":"https:\/\/materialparts.com\/zh\/wp-json\/wp\/v2\/comments?post=8000"}],"version-history":[{"count":1,"href":"https:\/\/materialparts.com\/zh\/wp-json\/wp\/v2\/posts\/8000\/revisions"}],"predecessor-version":[{"id":8139,"href":"https:\/\/materialparts.com\/zh\/wp-json\/wp\/v2\/posts\/8000\/revisions\/8139"}],"wp:attachment":[{"href":"https:\/\/materialparts.com\/zh\/wp-json\/wp\/v2\/media?parent=8000"}],"wp:term":[{"taxonomy":"category","embeddable":true,"href":"https:\/\/materialparts.com\/zh\/wp-json\/wp\/v2\/categories?post=8000"},{"taxonomy":"post_tag","embeddable":true,"href":"https:\/\/materialparts.com\/zh\/wp-json\/wp\/v2\/tags?post=8000"},{"taxonomy":"chip_brand","embeddable":true,"href":"https:\/\/materialparts.com\/zh\/wp-json\/wp\/v2\/chip_brand?post=8000"}],"curies":[{"name":"wp","href":"https:\/\/api.w.org\/{rel}","templated":true}]}}