{"id":7998,"date":"2026-06-28T06:38:10","date_gmt":"2026-06-28T06:38:10","guid":{"rendered":"https:\/\/materialparts.com\/sn74ls75n\/"},"modified":"2026-06-28T11:44:18","modified_gmt":"2026-06-28T11:44:18","slug":"sn74ls75n","status":"publish","type":"post","link":"https:\/\/materialparts.com\/zh\/sn74ls75n\/","title":{"rendered":"SN74LS75N"},"content":{"rendered":"

\u4ea7\u54c1\u6982\u89c8<\/h2>\n

The SN74LS75N from Texas Instruments is a 4-bit bistable transparent latch \u2014 the TTL counterpart of the CD4042, providing four D-type latches with complementary outputs in a 16-pin PDIP package.<\/p>\n

\u4e3b\u8981\u89c4\u683c<\/h2>\n\n\n\n\n\n\n\n\n\n\n\n\n
\u529f\u80fd<\/td>\n4-bit bistable transparent latch<\/td>\n<\/tr>\n
\u903b\u8f91\u5bb6\u65cf<\/td>\nLS (Low-power Schottky)<\/td>\n<\/tr>\n
\u7535\u6e90\u7535\u538b<\/td>\n4.75V to 5.25V<\/td>\n<\/tr>\n
Latches<\/td>\n4 (arranged as 2 pairs with 2 enable inputs)<\/td>\n<\/tr>\n
Enable Inputs<\/td>\n1C (enables latches 1&2), 2C (enables latches 3&4)<\/td>\n<\/tr>\n
Outputs<\/td>\nQ and Q\u0304 per latch (complementary)<\/td>\n<\/tr>\n
\u4f20\u64ad\u5ef6\u8fdf<\/td>\n14-30ns (D to Q)<\/td>\n<\/tr>\n
Setup Time<\/td>\n20ns minimum<\/td>\n<\/tr>\n
Hold Time<\/td>\n5ns minimum<\/td>\n<\/tr>\n
\u5de5\u4f5c\u6e29\u5ea6<\/td>\n0\u00b0C to +70\u00b0C<\/td>\n<\/tr>\n
\u5305\u88c5<\/td>\nPDIP-16 (19.3 x 6.35mm)<\/td>\n<\/tr>\n<\/table>\n

\u7279\u70b9<\/h2>\n
    \n
  • 4 D-type transparent latches<\/li>\n
  • Two enable inputs (each controls 2 latches)<\/li>\n
  • Complementary Q and Q\u0304 outputs<\/li>\n
  • Transparent: Q follows D while enable is HIGH<\/li>\n
  • Latched: Q holds when enable goes LOW<\/li>\n
  • Diode-clamped inputs<\/li>\n<\/ul>\n

    \u5e94\u7528<\/h2>\n
      \n
    • Data holding registers<\/li>\n
    • Address latching<\/li>\n
    • I\/O port buffering<\/li>\n
    • Indicator drivers<\/li>\n<\/ul>","protected":false},"excerpt":{"rendered":"

      Product Overview The SN74LS75N from Texas Instruments is a 4-bit bistable transparent latch \u2014 the TTL counterpart of the CD4042, providing four D-type latches with complementary outputs in a 16-pin PDIP package. Key Specifications Function 4-bit bistable transparent latch Logic Family LS (Low-power Schottky) Supply Voltage 4.75V to 5.25V Latches 4 (arranged as 2 pairs […]<\/p>\n","protected":false},"author":2,"featured_media":0,"comment_status":"open","ping_status":"","sticky":false,"template":"","format":"standard","meta":{"_acf_changed":false,"footnotes":""},"categories":[13,20],"tags":[],"chip_brand":[138],"class_list":["post-7998","post","type-post","status-publish","format-standard","hentry","category-integrated-circuits-ics","category-interface-ics","chip_brand-ti"],"acf":{"brief_explanation":"4-bit transparent latch, dual enables, complementary outputs, LS TTL, PDIP-16","date_code":"","package_case":"PDIP-16 (19.3 x 6.35 x 4.57mm, 2.54mm pitch, through-hole)","in_stock":3000,"datasheet":"https:\/\/www.ti.com\/lit\/ds\/symlink\/sn74ls75.pdf","price":"$0.50 @ 1ku","product_introduction":"The SN74LS75N from Texas Instruments is a 4-bit bistable transparent latch consisting of four D-type latches with two active-HIGH enable inputs. When the enable (C) is HIGH, the Q output follows the D input (transparent mode). When the enable goes LOW, the data present at D just before the transition is latched and held at Q. The four latches are arranged in two pairs: enable 1C controls latches 1 and 2; enable 2C controls latches 3 and 4. This dual-enable arrangement allows the 7475 to latch two 2-bit groups independently or one 4-bit group simultaneously (by tying 1C and 2C together). Each latch provides complementary Q and Q\u0304 outputs. The 7475 is the TTL equivalent of the CMOS CD4042 but without polarity control \u2014 it's always transparent when the enable is HIGH. The 30ns propagation delay and 20ns setup time make it suitable for medium-speed digital systems. The N suffix denotes the PDIP-16 through-hole package.","working_principle":"Each latch in the SN74LS75N operates as a transparent D latch. When the enable input (C) is HIGH: Q follows D in real time; Q\u0304 follows D\u0304 (complement of D). When C transitions from HIGH to LOW: the data present at D at the moment of transition is captured and held at Q; Q\u0304 holds the complement. When C remains LOW: Q and Q\u0304 hold their latched values regardless of changes at D. The two enable inputs (1C and 2C) each control a pair of latches: 1C controls latches 1 and 2 (pins 2D,3D \u2192 2Q,3Q); 2C controls latches 3 and 4 (pins 5D,6D \u2192 5Q,6Q). For 4-bit simultaneous latching: tie 1C and 2C together; all four latches capture on the same enable transition. For independent 2-bit latching: separate 1C and 2C; each pair captures at different times. The 20ns setup time means D must be stable at least 20ns before C goes LOW; the 5ns hold time means D must remain stable for 5ns after C goes LOW.","pin_description":"\n
      Pin<\/th>Name<\/th>Type<\/th>Description<\/th><\/tr>\n
      1<\/td>1Q\u0304<\/td>Output<\/td>Latch 1 complementary output<\/td><\/tr>\n
      2<\/td>1Q<\/td>Output<\/td>Latch 1 true output<\/td><\/tr>\n
      3<\/td>1D<\/td>Input<\/td>Latch 1 data input<\/td><\/tr>\n
      4<\/td>2D<\/td>Input<\/td>Latch 2 data input<\/td><\/tr>\n
      5<\/td>2Q<\/td>Output<\/td>Latch 2 true output<\/td><\/tr>\n
      6<\/td>2Q\u0304<\/td>Output<\/td>Latch 2 complementary output<\/td><\/tr>\n
      7<\/td>GND<\/td>Power<\/td>Ground<\/td><\/tr>\n
      8<\/td>3Q\u0304<\/td>Output<\/td>Latch 3 complementary output<\/td><\/tr>\n
      9<\/td>3Q<\/td>Output<\/td>Latch 3 true output<\/td><\/tr>\n
      10<\/td>3D<\/td>Input<\/td>Latch 3 data input<\/td><\/tr>\n
      11<\/td>4D<\/td>Input<\/td>Latch 4 data input<\/td><\/tr>\n
      12<\/td>4Q<\/td>Output<\/td>Latch 4 true output<\/td><\/tr>\n
      13<\/td>4Q\u0304<\/td>Output<\/td>Latch 4 complementary output<\/td><\/tr>\n
      14<\/td>2C<\/td>Input<\/td>Enable for latches 3 & 4 (active HIGH)<\/td><\/tr>\n
      15<\/td>1C<\/td>Input<\/td>Enable for latches 1 & 2 (active HIGH)<\/td><\/tr>\n
      16<\/td>VCC<\/td>Power<\/td>Supply (5V)<\/td><\/tr>\n<\/table>","application_scenarios":"
        \n
      • 4-Bit Data Latch:<\/strong> 4 data bits \u2192 1D,2D,3D,4D; 1C and 2C tied together; enable pulse captures all 4 bits simultaneously; Q outputs held stable<\/li>\n
      • 2+2 Independent Latching:<\/strong> 1C and 2C separate; 2-bit address latched by 1C; 2-bit data latched by 2C; independent timing<\/li>\n
      • Address Latch (8051):<\/td> Multiplexed AD0-AD3 \u2192 1D-4D; ALE \u2192 1C+2C; Q outputs = stable lower address bits<\/li>\n
      • Indicator Driver:<\/strong> System status bits \u2192 D inputs; enable from control logic; Q\u0304 drives active-LOW LED indicators; Q drives active-HIGH<\/li>\n<\/ul>","alternative_models":"\n
        Model<\/th>Manufacturer<\/th>Key Difference<\/th>Package<\/th>Supply<\/th><\/tr>\n
        74LS75N<\/td>TI\/Nexperia<\/td>Original TTL version with 5V-only supply, typical propagation delay 10-15ns<\/td>DIP-16<\/td>5V TTL<\/td><\/tr>\n
        74LS75D<\/td>TI\/Nexperia<\/td>Surface-mount SOIC version of LS with identical logic function<\/td>SOIC-16<\/td>5V TTL<\/td><\/tr>\n
        74HC75D<\/td>TI\/Nexperia<\/td>CMOS version with wide 2-6V supply range, lower power consumption and higher noise immunity<\/td>SOIC-16<\/td>2-6V CMOS<\/td><\/tr>\n
        74HC75N<\/td>TI\/Nexperia<\/td>Through-hole DIP version of HC family for prototyping and repair<\/td>DIP-16<\/td>2-6V CMOS<\/td><\/tr>\n
        74HCT75D<\/td>TI\/Nexperia<\/td>CMOS with TTL-compatible input levels, ideal for mixing with LS devices at 5V<\/td>SOIC-16<\/td>4.5-5.5V TTL-in<\/td><\/tr>\n
        74HCT75N<\/td>TI\/Nexperia<\/td>Through-hole DIP version of HCT family for prototyping and repair<\/td>DIP-16<\/td>4.5-5.5V TTL-in<\/td><\/tr>\n<\/table>\n

        The 7475 is a 4-Bit Bistable Latch. Family variants span from the original LS TTL (5V only) to modern LVC\/AUP (down to 0.8V). HC and HCT versions offer 2-6V CMOS operation with HCT providing TTL-compatible input thresholds for mixed 5V systems. CD4000-series equivalents offer the widest 3-18V supply range at the cost of lower switching speed. DIP packages (N suffix) are through-hole; SOIC (D suffix) and TSSOP are surface-mount.<\/p>"},"_links":{"self":[{"href":"https:\/\/materialparts.com\/zh\/wp-json\/wp\/v2\/posts\/7998","targetHints":{"allow":["GET"]}}],"collection":[{"href":"https:\/\/materialparts.com\/zh\/wp-json\/wp\/v2\/posts"}],"about":[{"href":"https:\/\/materialparts.com\/zh\/wp-json\/wp\/v2\/types\/post"}],"author":[{"embeddable":true,"href":"https:\/\/materialparts.com\/zh\/wp-json\/wp\/v2\/users\/2"}],"replies":[{"embeddable":true,"href":"https:\/\/materialparts.com\/zh\/wp-json\/wp\/v2\/comments?post=7998"}],"version-history":[{"count":1,"href":"https:\/\/materialparts.com\/zh\/wp-json\/wp\/v2\/posts\/7998\/revisions"}],"predecessor-version":[{"id":8140,"href":"https:\/\/materialparts.com\/zh\/wp-json\/wp\/v2\/posts\/7998\/revisions\/8140"}],"wp:attachment":[{"href":"https:\/\/materialparts.com\/zh\/wp-json\/wp\/v2\/media?parent=7998"}],"wp:term":[{"taxonomy":"category","embeddable":true,"href":"https:\/\/materialparts.com\/zh\/wp-json\/wp\/v2\/categories?post=7998"},{"taxonomy":"post_tag","embeddable":true,"href":"https:\/\/materialparts.com\/zh\/wp-json\/wp\/v2\/tags?post=7998"},{"taxonomy":"chip_brand","embeddable":true,"href":"https:\/\/materialparts.com\/zh\/wp-json\/wp\/v2\/chip_brand?post=7998"}],"curies":[{"name":"wp","href":"https:\/\/api.w.org\/{rel}","templated":true}]}}