{"id":7995,"date":"2026-06-28T06:32:27","date_gmt":"2026-06-28T06:32:27","guid":{"rendered":"https:\/\/materialparts.com\/sn74ls164n\/"},"modified":"2026-06-28T11:44:23","modified_gmt":"2026-06-28T11:44:23","slug":"sn74ls164n","status":"publish","type":"post","link":"https:\/\/materialparts.com\/zh\/sn74ls164n\/","title":{"rendered":"SN74LS164N"},"content":{"rendered":"<h2>\u4ea7\u54c1\u6982\u89c8<\/h2>\n<p>The SN74LS164N from Texas Instruments is an 8-bit serial-in parallel-out shift register \u2014 the TTL equivalent of the CD4094, ideal for expanding microcontroller outputs from 2 pins to 8 in a 14-pin PDIP package.<\/p>\n<h2>\u4e3b\u8981\u89c4\u683c<\/h2>\n<table>\n<tr>\n<td>\u529f\u80fd<\/td>\n<td>8-bit serial-in parallel-out shift register<\/td>\n<\/tr>\n<tr>\n<td>\u903b\u8f91\u5bb6\u65cf<\/td>\n<td>LS (Low-power Schottky)<\/td>\n<\/tr>\n<tr>\n<td>\u7535\u6e90\u7535\u538b<\/td>\n<td>4.75V to 5.25V<\/td>\n<\/tr>\n<tr>\n<td>Serial Inputs<\/td>\n<td>A and B (both must be HIGH to shift in 1)<\/td>\n<\/tr>\n<tr>\n<td>Outputs<\/td>\n<td>Q0-Q7 (8 parallel outputs)<\/td>\n<\/tr>\n<tr>\n<td>Clear<\/td>\n<td>Asynchronous, active-LOW (CLR)<\/td>\n<\/tr>\n<tr>\n<td>Trigger<\/td>\n<td>Positive edge on CLK<\/td>\n<\/tr>\n<tr>\n<td>Max Clock Frequency<\/td>\n<td>25MHz typical<\/td>\n<\/tr>\n<tr>\n<td>\u5de5\u4f5c\u6e29\u5ea6<\/td>\n<td>0\u00b0C to +70\u00b0C<\/td>\n<\/tr>\n<tr>\n<td>\u5305\u88c5<\/td>\n<td>PDIP-14 (19.3 x 6.35mm)<\/td>\n<\/tr>\n<\/table>\n<h2>\u7279\u70b9<\/h2>\n<ul>\n<li>8-bit serial-to-parallel conversion<\/li>\n<li>Gated serial inputs (A AND B both HIGH = shift in 1)<\/li>\n<li>Asynchronous clear (CLR, active-LOW)<\/li>\n<li>Cascadable (Q7 \u2192 next A input)<\/li>\n<li>25MHz clock rate<\/li>\n<\/ul>\n<h2>\u5e94\u7528<\/h2>\n<ul>\n<li>GPIO expansion (2 pins \u2192 8 outputs)<\/li>\n<li>LED chaser \/ display driver<\/li>\n<li>Serial-to-parallel data conversion<\/li>\n<li>Multi-chip display multiplexing<\/li>\n<\/ul>","protected":false},"excerpt":{"rendered":"<p>Product Overview The SN74LS164N from Texas Instruments is an 8-bit serial-in parallel-out shift register \u2014 the TTL equivalent of the CD4094, ideal for expanding microcontroller outputs from 2 pins to 8 in a 14-pin PDIP package. Key Specifications Function 8-bit serial-in parallel-out shift register Logic Family LS (Low-power Schottky) Supply Voltage 4.75V to 5.25V Serial [&hellip;]<\/p>\n","protected":false},"author":2,"featured_media":0,"comment_status":"open","ping_status":"","sticky":false,"template":"","format":"standard","meta":{"_acf_changed":false,"footnotes":""},"categories":[13,20],"tags":[],"chip_brand":[138],"class_list":["post-7995","post","type-post","status-publish","format-standard","hentry","category-integrated-circuits-ics","category-interface-ics","chip_brand-ti"],"acf":{"brief_explanation":"8-bit serial-in parallel-out shift register, LS TTL, PDIP-14","date_code":"","package_case":"PDIP-14 (19.3 x 6.35 x 4.57mm, 2.54mm pitch, through-hole)","in_stock":5000,"datasheet":"https:\/\/www.ti.com\/lit\/ds\/symlink\/sn74ls164.pdf","price":"$0.40 @ 1ku","product_introduction":"The SN74LS164N from Texas Instruments is an 8-bit serial-in parallel-out shift register. Data is shifted in serially through the A and B gated inputs on each rising clock edge, and appears as 8 parallel outputs (Q0-Q7) after 8 clock cycles. The two serial inputs (A and B) are ANDed internally: a 1 is shifted in only when both A AND B are HIGH. This gating feature allows one input to serve as an active-HIGH enable while the other carries data \u2014 if either is LOW, a 0 is shifted in. The asynchronous clear (CLR=LOW) immediately resets all outputs to 0. For cascading, Q7 of one 74164 connects to the A input of the next; 2 chips give 16 outputs from 2 MCU pins (DATA + CLK). Unlike the 74HC595 which has an output latch and 3-state outputs, the 74164's outputs update immediately as data shifts through \u2014 each output toggles as the shift register fills, which can cause flicker in display applications. The 74164 is simpler and cheaper than the 595, making it ideal for LED chasers and non-critical output expansion. The N suffix denotes the PDIP-14 through-hole package.","working_principle":"The SN74LS164N shifts data on each rising clock edge. The data shifted in is the AND of inputs A and B: if both are HIGH, a 1 enters; if either is LOW, a 0 enters. On each rising CLK edge: Q0 takes the value of (A AND B); Q1 takes the old value of Q0; Q2 takes old Q1; ... Q7 takes old Q6. After 8 clock cycles, 8 bits of serial data have been converted to 8 parallel outputs. The clear input (CLR=LOW) asynchronously forces all Q0-Q7 to 0 regardless of CLK. For normal operation, CLR must be HIGH. The gated inputs allow: A=data, B=enable (or vice versa); data is shifted in only when enable is HIGH; when enable is LOW, zeros are shifted in regardless of A. For cascading: Q7 \u2192 A of next 74164; B of all chips tied HIGH; shared CLK; shared CLR; 2 chips = 16 outputs, 3 chips = 24 outputs, all from 2 MCU pins. Unlike the 74HC595, the 74164 has no output latch: outputs change as data shifts through, so LED displays may flicker during shifting. For static displays, use the 74HC595 instead.","pin_description":"<table border=\"1\" cellpadding=\"4\">\n<tr><th>Pin<\/th><th>Name<\/th><th>Type<\/th><th>Description<\/th><\/tr>\n<tr><td>1<\/td><td>A<\/td><td>Input<\/td><td>Serial input A (gated with B)<\/td><\/tr>\n<tr><td>2<\/td><td>B<\/td><td>Input<\/td><td>Serial input B (gated with A)<\/td><\/tr>\n<tr><td>3<\/td><td>Q0<\/td><td>Output<\/td><td>Parallel output bit 0 (first shift stage)<\/td><\/tr>\n<tr><td>4<\/td><td>Q1<\/td><td>Output<\/td><td>Parallel output bit 1<\/td><\/tr>\n<tr><td>5<\/td><td>Q2<\/td><td>Output<\/td><td>Parallel output bit 2<\/td><\/tr>\n<tr><td>6<\/td><td>Q3<\/td><td>Output<\/td><td>Parallel output bit 3<\/td><\/tr>\n<tr><td>7<\/td><td>GND<\/td><td>Power<\/td><td>Ground<\/td><\/tr>\n<tr><td>8<\/td><td>CLK<\/td><td>Input<\/td><td>Clock (positive edge)<\/td><\/tr>\n<tr><td>9<\/td><td>CLR<\/td><td>Input<\/td><td>Clear (active LOW, resets all outputs to 0)<\/td><\/tr>\n<tr><td>10<\/td><td>Q4<\/td><td>Output<\/td><td>Parallel output bit 4<\/td><\/tr>\n<tr><td>11<\/td><td>Q5<\/td><td>Output<\/td><td>Parallel output bit 5<\/td><\/tr>\n<tr><td>12<\/td><td>Q6<\/td><td>Output<\/td><td>Parallel output bit 6<\/td><\/tr>\n<tr><td>13<\/td><td>Q7<\/td><td>Output<\/td><td>Parallel output bit 7 (last stage, for cascading)<\/td><\/tr>\n<tr><td>14<\/td><td>VCC<\/td><td>Power<\/td><td>Supply (5V)<\/td><\/tr>\n<\/table>","application_scenarios":"<ul>\n<li><strong>LED Chaser:<\/strong> MCU: DATA \u2192 A; CLK \u2192 CLK; CLR \u2192 HIGH; shift pattern: 10000000 \u2192 01000000 \u2192 00100000 \u2192 etc.; Q0-Q7 drive 8 LEDs; chasing effect<\/li>\n<li><strong>16-Output Expansion:<\/strong> Two 74164s; Q7(#1) \u2192 A(#2); shared CLK, B=HIGH, CLR=HIGH; 16 outputs from 2 MCU pins<\/li>\n<li><strong>7-Segment Multiplex:<\/strong> 74164 shifts segment data; common anode displays driven sequentially; one digit at a time<\/li>\n<li><strong>Gated Input:<\/strong> A=serial data, B=enable; shift in data only when B=HIGH; shift in zeros when B=LOW; selective data entry<\/li>\n<\/ul>","alternative_models":"<table border=\"1\" cellpadding=\"4\">\n<tr><th>Model<\/th><th>Manufacturer<\/th><th>Key Difference<\/th><th>Package<\/th><th>Supply<\/th><\/tr>\n<tr><td>74LS164N<\/td><td>TI\/Nexperia<\/td><td>Original TTL version with 5V-only supply, typical propagation delay 10-15ns<\/td><td>DIP-14<\/td><td>5V TTL<\/td><\/tr>\n<tr><td>74LS164D<\/td><td>TI\/Nexperia<\/td><td>Surface-mount SOIC version of LS with identical logic function<\/td><td>SOIC-14<\/td><td>5V TTL<\/td><\/tr>\n<tr><td>74HC164D<\/td><td>TI\/Nexperia<\/td><td>CMOS version with wide 2-6V supply range, lower power consumption and higher noise immunity<\/td><td>SOIC-14<\/td><td>2-6V CMOS<\/td><\/tr>\n<tr><td>74HC164N<\/td><td>TI\/Nexperia<\/td><td>Through-hole DIP version of HC family for prototyping and repair<\/td><td>DIP-14<\/td><td>2-6V CMOS<\/td><\/tr>\n<tr><td>74HCT164D<\/td><td>TI\/Nexperia<\/td><td>CMOS with TTL-compatible input levels, ideal for mixing with LS devices at 5V<\/td><td>SOIC-14<\/td><td>4.5-5.5V TTL-in<\/td><\/tr>\n<tr><td>74HCT164N<\/td><td>TI\/Nexperia<\/td><td>Through-hole DIP version of HCT family for prototyping and repair<\/td><td>DIP-14<\/td><td>4.5-5.5V TTL-in<\/td><\/tr>\n<\/table>\n<p>The 74164 is a 8-Bit Parallel-Out Serial Shift Register. Family variants span from the original LS TTL (5V only) to modern LVC\/AUP (down to 0.8V). HC and HCT versions offer 2-6V CMOS operation with HCT providing TTL-compatible input thresholds for mixed 5V systems. CD4000-series equivalents offer the widest 3-18V supply range at the cost of lower switching speed. DIP packages (N suffix) are through-hole; SOIC (D suffix) and TSSOP are surface-mount.<\/p>"},"_links":{"self":[{"href":"https:\/\/materialparts.com\/zh\/wp-json\/wp\/v2\/posts\/7995","targetHints":{"allow":["GET"]}}],"collection":[{"href":"https:\/\/materialparts.com\/zh\/wp-json\/wp\/v2\/posts"}],"about":[{"href":"https:\/\/materialparts.com\/zh\/wp-json\/wp\/v2\/types\/post"}],"author":[{"embeddable":true,"href":"https:\/\/materialparts.com\/zh\/wp-json\/wp\/v2\/users\/2"}],"replies":[{"embeddable":true,"href":"https:\/\/materialparts.com\/zh\/wp-json\/wp\/v2\/comments?post=7995"}],"version-history":[{"count":1,"href":"https:\/\/materialparts.com\/zh\/wp-json\/wp\/v2\/posts\/7995\/revisions"}],"predecessor-version":[{"id":8143,"href":"https:\/\/materialparts.com\/zh\/wp-json\/wp\/v2\/posts\/7995\/revisions\/8143"}],"wp:attachment":[{"href":"https:\/\/materialparts.com\/zh\/wp-json\/wp\/v2\/media?parent=7995"}],"wp:term":[{"taxonomy":"category","embeddable":true,"href":"https:\/\/materialparts.com\/zh\/wp-json\/wp\/v2\/categories?post=7995"},{"taxonomy":"post_tag","embeddable":true,"href":"https:\/\/materialparts.com\/zh\/wp-json\/wp\/v2\/tags?post=7995"},{"taxonomy":"chip_brand","embeddable":true,"href":"https:\/\/materialparts.com\/zh\/wp-json\/wp\/v2\/chip_brand?post=7995"}],"curies":[{"name":"wp","href":"https:\/\/api.w.org\/{rel}","templated":true}]}}