{"id":7972,"date":"2026-06-28T06:17:42","date_gmt":"2026-06-28T06:17:42","guid":{"rendered":"https:\/\/materialparts.com\/sn74ls126n\/"},"modified":"2026-06-28T11:44:59","modified_gmt":"2026-06-28T11:44:59","slug":"sn74ls126n","status":"publish","type":"post","link":"https:\/\/materialparts.com\/zh\/sn74ls126n\/","title":{"rendered":"SN74LS126N"},"content":{"rendered":"

\u4ea7\u54c1\u6982\u89c8<\/h2>\n

The SN74LS126N from Texas Instruments contains four independent bus buffer gates with 3-state outputs and active-HIGH output enable, designed for bus-oriented systems in a 14-pin PDIP package.<\/p>\n

\u4e3b\u8981\u89c4\u683c<\/h2>\n\n\n\n\n\n\n\n\n\n\n
Number of Gates<\/td>\n4 (quad bus buffer, 3-state)<\/td>\n<\/tr>\n
\u903b\u8f91\u5bb6\u65cf<\/td>\nLS (Low-power Schottky)<\/td>\n<\/tr>\n
\u7535\u6e90\u7535\u538b<\/td>\n4.75V to 5.25V<\/td>\n<\/tr>\n
Output Enable<\/td>\nActive-HIGH (HIGH=enabled, LOW=high-Z)<\/td>\n<\/tr>\n
\u4f20\u64ad\u5ef6\u8fdf<\/td>\n9ns typical<\/td>\n<\/tr>\n
Output Drive (IOL\/IOH)<\/td>\n24mA \/ -2.6mA (bus driver)<\/td>\n<\/tr>\n
3-State Output Current<\/td>\n20\u00b5A max (high-Z leakage)<\/td>\n<\/tr>\n
\u5de5\u4f5c\u6e29\u5ea6<\/td>\n0\u00b0C to +70\u00b0C<\/td>\n<\/tr>\n
\u5305\u88c5<\/td>\nPDIP-14 (19.3 x 6.35mm)<\/td>\n<\/tr>\n<\/table>\n

\u7279\u70b9<\/h2>\n
    \n
  • Four non-inverting bus buffers with 3-state outputs<\/li>\n
  • Active-HIGH output enable<\/li>\n
  • 24mA output sink current \u2014 bus driver capability<\/li>\n
  • High-Z state when disabled (only 20\u00b5A leakage)<\/li>\n
  • Complement to 74125 (active-LOW enable)<\/li>\n<\/ul>\n

    \u5e94\u7528<\/h2>\n
      \n
    • Microprocessor bus interface<\/li>\n
    • Multi-device shared bus<\/li>\n
    • I\/O port expansion<\/li>\n
    • Data routing and isolation<\/li>\n<\/ul>","protected":false},"excerpt":{"rendered":"

      Product Overview The SN74LS126N from Texas Instruments contains four independent bus buffer gates with 3-state outputs and active-HIGH output enable, designed for bus-oriented systems in a 14-pin PDIP package. Key Specifications Number of Gates 4 (quad bus buffer, 3-state) Logic Family LS (Low-power Schottky) Supply Voltage 4.75V to 5.25V Output Enable Active-HIGH (HIGH=enabled, LOW=high-Z) Propagation […]<\/p>\n","protected":false},"author":2,"featured_media":0,"comment_status":"open","ping_status":"","sticky":false,"template":"","format":"standard","meta":{"_acf_changed":false,"footnotes":""},"categories":[13,20],"tags":[],"chip_brand":[138],"class_list":["post-7972","post","type-post","status-publish","format-standard","hentry","category-integrated-circuits-ics","category-interface-ics","chip_brand-ti"],"acf":{"brief_explanation":"Quad 3-state bus buffer, active-HIGH enable, LS TTL, PDIP-14","date_code":"","package_case":"PDIP-14 (19.3 x 6.35 x 4.57mm, 2.54mm pitch, through-hole)","in_stock":5000,"datasheet":"https:\/\/www.ti.com\/lit\/ds\/symlink\/sn74ls126a.pdf","price":"$0.30 @ 1ku","product_introduction":"The SN74LS126N from Texas Instruments contains four independent non-inverting buffer gates with 3-state (high-impedance) outputs controlled by active-HIGH enable pins. When the output enable (OE) is HIGH, the buffer passes data from input to output with no inversion: Y = A. When OE is LOW, the output enters a high-impedance (high-Z) state, effectively disconnecting from the bus \u2014 only 20\u00b5A of leakage current flows. This 3-state capability is essential for bus-oriented systems where multiple devices share a common data bus: only one device drives the bus at a time (OE=HIGH), while all others are in high-Z (OE=LOW). The 24mA sink capability makes the 74126 suitable for driving heavily loaded bus lines. The active-HIGH enable is the complement of the 74125 (active-LOW enable). The N suffix denotes the PDIP-14 through-hole package.","working_principle":"Each buffer in the SN74LS126N has two inputs: a data input (A) and an output enable (OE). When OE=HIGH, the output Y follows input A (non-inverting): Y = A. When OE=LOW, the output transistors are both turned off, placing the output in a high-impedance state where it neither sources nor sinks significant current (<20\u00b5A). In a bus system, the 74126 serves as a 'gate' that connects or disconnects a device from the shared bus. A decoder (like 74LS138) generates the enable signals, ensuring only one 74126 is active at any time. If two buffers drive the bus simultaneously with conflicting data, a bus contention occurs \u2014 large current flows between the conflicting outputs, potentially damaging the devices. The 74126's 24mA sink capability means it can drive long PCB traces or backplane bus lines with significant capacitive loading. The 9ns propagation delay is fast enough for microprocessor bus cycles.","pin_description":"\n
      Pin<\/th>Name<\/th>Type<\/th>Description<\/th><\/tr>\n
      1<\/td>1OE<\/td>Input<\/td>Gate 1 output enable (active HIGH)<\/td><\/tr>\n
      2<\/td>1A<\/td>Input<\/td>Gate 1 data input<\/td><\/tr>\n
      3<\/td>1Y<\/td>Output<\/td>Gate 1 output (3-state)<\/td><\/tr>\n
      4<\/td>2OE<\/td>Input<\/td>Gate 2 output enable<\/td><\/tr>\n
      5<\/td>2A<\/td>Input<\/td>Gate 2 data input<\/td><\/tr>\n
      6<\/td>2Y<\/td>Output<\/td>Gate 2 output (3-state)<\/td><\/tr>\n
      7<\/td>GND<\/td>Power<\/td>Ground<\/td><\/tr>\n
      8<\/td>3Y<\/td>Output<\/td>Gate 3 output (3-state)<\/td><\/tr>\n
      9<\/td>3A<\/td>Input<\/td>Gate 3 data input<\/td><\/tr>\n
      10<\/td>3OE<\/td>Input<\/td>Gate 3 output enable<\/td><\/tr>\n
      11<\/td>4Y<\/td>Output<\/td>Gate 4 output (3-state)<\/td><\/tr>\n
      12<\/td>4A<\/td>Input<\/td>Gate 4 data input<\/td><\/tr>\n
      13<\/td>4OE<\/td>Input<\/td>Gate 4 output enable<\/td><\/tr>\n
      14<\/td>VCC<\/td>Power<\/td>Supply (5V)<\/td><\/tr>\n<\/table>","application_scenarios":"
        \n
      • 4-Bit Bus Interface:<\/strong> 4 data bits from peripheral \u2192 74126 inputs; decoder generates OE for one device at a time; shared bus \u2192 CPU<\/li>\n
      • Output Port:<\/strong> CPU data bus \u2192 74126 inputs; OE tied to I\/O write signal; 74126 outputs drive external devices when CPU writes<\/li>\n
      • Bus Isolation:<\/strong> When system not accessing a module, OE=LOW \u2192 module's 74126 outputs float; no bus loading<\/li>\n
      • With 74LS125:<\/strong> Mix 74126 (active-HIGH OE) and 74125 (active-LOW OE) for different enable polarities in same bus system<\/li>\n<\/ul>","alternative_models":"\n
        Model<\/th>Manufacturer<\/th>Key Difference<\/th>Package<\/th>Supply<\/th><\/tr>\n
        74LS126N<\/td>TI\/Nexperia<\/td>Original TTL version with 5V-only supply, typical propagation delay 10-15ns<\/td>DIP-14<\/td>5V TTL<\/td><\/tr>\n
        74LS126D<\/td>TI\/Nexperia<\/td>Surface-mount SOIC version of LS with identical logic function<\/td>SOIC-14<\/td>5V TTL<\/td><\/tr>\n
        74HC126D<\/td>TI\/Nexperia<\/td>CMOS version with wide 2-6V supply range, lower power consumption and higher noise immunity<\/td>SOIC-14<\/td>2-6V CMOS<\/td><\/tr>\n
        74HC126N<\/td>TI\/Nexperia<\/td>Through-hole DIP version of HC family for prototyping and repair<\/td>DIP-14<\/td>2-6V CMOS<\/td><\/tr>\n
        74HCT126D<\/td>TI\/Nexperia<\/td>CMOS with TTL-compatible input levels, ideal for mixing with LS devices at 5V<\/td>SOIC-14<\/td>4.5-5.5V TTL-in<\/td><\/tr>\n
        74HCT126N<\/td>TI\/Nexperia<\/td>Through-hole DIP version of HCT family for prototyping and repair<\/td>DIP-14<\/td>4.5-5.5V TTL-in<\/td><\/tr>\n
        74LVC126D<\/td>TI\/Nexperia<\/td>Low-voltage CMOS for 1.65-3.6V modern logic with 24mA output drive and bus-hold inputs<\/td>SOIC-14<\/td>1.65-3.6V CMOS<\/td><\/tr>\n
        74LVC126N<\/td>TI\/Nexperia<\/td>Through-hole DIP version of LVC family for prototyping and repair<\/td>DIP-14<\/td>1.65-3.6V CMOS<\/td><\/tr>\n<\/table>\n

        The 74126 is a Quad Bus Buffer with 3-State Output (Active-High Enable). Family variants span from the original LS TTL (5V only) to modern LVC\/AUP (down to 0.8V). HC and HCT versions offer 2-6V CMOS operation with HCT providing TTL-compatible input thresholds for mixed 5V systems. CD4000-series equivalents offer the widest 3-18V supply range at the cost of lower switching speed. DIP packages (N suffix) are through-hole; SOIC (D suffix) and TSSOP are surface-mount.<\/p>"},"_links":{"self":[{"href":"https:\/\/materialparts.com\/zh\/wp-json\/wp\/v2\/posts\/7972","targetHints":{"allow":["GET"]}}],"collection":[{"href":"https:\/\/materialparts.com\/zh\/wp-json\/wp\/v2\/posts"}],"about":[{"href":"https:\/\/materialparts.com\/zh\/wp-json\/wp\/v2\/types\/post"}],"author":[{"embeddable":true,"href":"https:\/\/materialparts.com\/zh\/wp-json\/wp\/v2\/users\/2"}],"replies":[{"embeddable":true,"href":"https:\/\/materialparts.com\/zh\/wp-json\/wp\/v2\/comments?post=7972"}],"version-history":[{"count":1,"href":"https:\/\/materialparts.com\/zh\/wp-json\/wp\/v2\/posts\/7972\/revisions"}],"predecessor-version":[{"id":8163,"href":"https:\/\/materialparts.com\/zh\/wp-json\/wp\/v2\/posts\/7972\/revisions\/8163"}],"wp:attachment":[{"href":"https:\/\/materialparts.com\/zh\/wp-json\/wp\/v2\/media?parent=7972"}],"wp:term":[{"taxonomy":"category","embeddable":true,"href":"https:\/\/materialparts.com\/zh\/wp-json\/wp\/v2\/categories?post=7972"},{"taxonomy":"post_tag","embeddable":true,"href":"https:\/\/materialparts.com\/zh\/wp-json\/wp\/v2\/tags?post=7972"},{"taxonomy":"chip_brand","embeddable":true,"href":"https:\/\/materialparts.com\/zh\/wp-json\/wp\/v2\/chip_brand?post=7972"}],"curies":[{"name":"wp","href":"https:\/\/api.w.org\/{rel}","templated":true}]}}