{"id":7950,"date":"2026-06-28T06:01:50","date_gmt":"2026-06-28T06:01:50","guid":{"rendered":"https:\/\/materialparts.com\/sn74ls32n-2\/"},"modified":"2026-06-28T11:45:23","modified_gmt":"2026-06-28T11:45:23","slug":"sn74ls32n-2","status":"publish","type":"post","link":"https:\/\/materialparts.com\/zh\/sn74ls32n-2\/","title":{"rendered":"SN74LS32N"},"content":{"rendered":"

\u4ea7\u54c1\u6982\u89c8<\/h2>\n

The SN74LS32N from Texas Instruments is a quad 2-input positive OR gate with LS TTL technology, 14ns propagation delay, and industry-standard 7432 pinout in a 14-pin PDIP package.<\/p>\n

\u4e3b\u8981\u89c4\u683c<\/h2>\n\n\n\n\n\n\n\n\n
Number of Gates<\/td>\n4 (quad 2-input OR)<\/td>\n<\/tr>\n
\u903b\u8f91\u5bb6\u65cf<\/td>\nLS (Low-power Schottky)<\/td>\n<\/tr>\n
\u7535\u6e90\u7535\u538b<\/td>\n4.75V to 5.25V (5V nominal)<\/td>\n<\/tr>\n
\u4f20\u64ad\u5ef6\u8fdf<\/td>\n14ns typical @ 5V<\/td>\n<\/tr>\n
Output Drive (IOL\/IOH)<\/td>\n8mA \/ -0.4mA<\/td>\n<\/tr>\n
\u5de5\u4f5c\u6e29\u5ea6<\/td>\n0\u00b0C to +70\u00b0C<\/td>\n<\/tr>\n
\u5305\u88c5<\/td>\nPDIP-14 (19.3 x 6.35mm)<\/td>\n<\/tr>\n<\/table>\n

\u7279\u70b9<\/h2>\n
    \n
  • Four independent 2-input OR gates<\/li>\n
  • LS TTL technology<\/li>\n
  • 14ns typical propagation delay<\/li>\n
  • Industry-standard 7432 pinout<\/li>\n<\/ul>\n

    \u5e94\u7528<\/h2>\n
      \n
    • Signal combining (any-input-active detection)<\/li>\n
    • Interrupt request lines<\/li>\n
    • Error flag combination<\/li>\n
    • Active-HIGH logic merging<\/li>\n<\/ul>","protected":false},"excerpt":{"rendered":"

      Product Overview The SN74LS32N from Texas Instruments is a quad 2-input positive OR gate with LS TTL technology, 14ns propagation delay, and industry-standard 7432 pinout in a 14-pin PDIP package. Key Specifications Number of Gates 4 (quad 2-input OR) Logic Family LS (Low-power Schottky) Supply Voltage 4.75V to 5.25V (5V nominal) Propagation Delay 14ns typical […]<\/p>\n","protected":false},"author":2,"featured_media":0,"comment_status":"open","ping_status":"","sticky":false,"template":"","format":"standard","meta":{"_acf_changed":false,"footnotes":""},"categories":[13,20],"tags":[],"chip_brand":[138],"class_list":["post-7950","post","type-post","status-publish","format-standard","hentry","category-integrated-circuits-ics","category-interface-ics","chip_brand-ti"],"acf":{"brief_explanation":"Quad 2-input OR gate, LS TTL, 14ns, PDIP-14","date_code":"","package_case":"PDIP-14 (19.3 x 6.35 x 4.57mm, 2.54mm pitch, through-hole)","in_stock":7000,"datasheet":"https:\/\/www.ti.com\/lit\/ds\/symlink\/sn74ls32.pdf","price":"$0.28 @ 1ku","product_introduction":"The SN74LS32N from Texas Instruments contains four independent 2-input OR gates in a 14-pin PDIP package. Each gate performs Y = A OR B; the output is HIGH when either or both inputs are HIGH, and LOW only when both inputs are LOW. The OR gate is the natural complement of the AND gate: while AND requires all inputs to be active, OR requires any input to be active. This makes the 7432 ideal for combining multiple active-HIGH signals: interrupt request lines, error flags, or enable signals. When any one of multiple sources needs to trigger an action, the OR gate combines them into a single output. The N suffix denotes the PDIP-14 through-hole package.","working_principle":"Each OR gate in the SN74LS32N performs Y = A OR B. The truth table is: 00\u21920, 01\u21921, 10\u21921, 11\u21921. The output is HIGH when at least one input is HIGH. The OR can be constructed from NAND gates using DeMorgan's theorem: A OR B = NOT(NOT-A AND NOT-B) = NAND(NAND(A,A), NAND(B,B)), but the dedicated 7432 is simpler and faster. For active-LOW signals (where LOW means active), use a NAND gate instead: if two active-LOW interrupt lines \/INT1 and \/INT2 need to be combined, NAND gives an active-LOW output when either input is LOW, which is the OR function in negative logic. The OR gate is also used in sum-of-products logic: A OR B = A+B in Boolean algebra, where + represents OR.","pin_description":"\n
      Pin<\/th>Name<\/th>Type<\/th>Description<\/th><\/tr>\n
      1<\/td>1A<\/td>Input<\/td>Gate 1 input A<\/td><\/tr>\n
      2<\/td>1B<\/td>Input<\/td>Gate 1 input B<\/td><\/tr>\n
      3<\/td>1Y<\/td>Output<\/td>Gate 1 output (OR)<\/td><\/tr>\n
      4<\/td>2A<\/td>Input<\/td>Gate 2 input A<\/td><\/tr>\n
      5<\/td>2B<\/td>Input<\/td>Gate 2 input B<\/td><\/tr>\n
      6<\/td>2Y<\/td>Output<\/td>Gate 2 output (OR)<\/td><\/tr>\n
      7<\/td>GND<\/td>Power<\/td>Ground<\/td><\/tr>\n
      8<\/td>3Y<\/td>Output<\/td>Gate 3 output (OR)<\/td><\/tr>\n
      9<\/td>3A<\/td>Input<\/td>Gate 3 input A<\/td><\/tr>\n
      10<\/td>3B<\/td>Input<\/td>Gate 3 input B<\/td><\/tr>\n
      11<\/td>4Y<\/td>Output<\/td>Gate 4 output (OR)<\/td><\/tr>\n
      12<\/td>4A<\/td>Input<\/td>Gate 4 input A<\/td><\/tr>\n
      13<\/td>4B<\/td>Input<\/td>Gate 4 input B<\/td><\/tr>\n
      14<\/td>VCC<\/td>Power<\/td>Supply (4.75V to 5.25V)<\/td><\/tr>\n<\/table>","application_scenarios":"
        \n
      • Interrupt Combine:<\/strong> \/INT1 and \/INT2 are active-HIGH; OR combines them; any interrupt triggers MCU<\/li>\n
      • Error Flag:<\/strong> Over-temp OR over-current OR over-voltage \u2192 single ERROR output; any fault triggers shutdown<\/li>\n
      • Clock Select:<\/strong> CLK_A or CLK_B \u2192 single output; one at a time (mutually exclusive clocks)<\/li>\n
      • Enable OR:<\/strong> Manual-enable OR software-enable; either one activates the circuit<\/li>\n<\/ul>","alternative_models":"\n
        Model<\/th>Manufacturer<\/th>Key Difference<\/th>Package<\/th>Supply<\/th><\/tr>\n
        74LS32N<\/td>TI\/Nexperia<\/td>Original TTL version with 5V-only supply, typical propagation delay 10-15ns<\/td>DIP-14<\/td>5V TTL<\/td><\/tr>\n
        74LS32D<\/td>TI\/Nexperia<\/td>Surface-mount SOIC version of LS with identical logic function<\/td>SOIC-14<\/td>5V TTL<\/td><\/tr>\n
        74HC32D<\/td>TI\/Nexperia<\/td>CMOS version with wide 2-6V supply range, lower power consumption and higher noise immunity<\/td>SOIC-14<\/td>2-6V CMOS<\/td><\/tr>\n
        74HC32N<\/td>TI\/Nexperia<\/td>Through-hole DIP version of HC family for prototyping and repair<\/td>DIP-14<\/td>2-6V CMOS<\/td><\/tr>\n
        74HCT32D<\/td>TI\/Nexperia<\/td>CMOS with TTL-compatible input levels, ideal for mixing with LS devices at 5V<\/td>SOIC-14<\/td>4.5-5.5V TTL-in<\/td><\/tr>\n
        74HCT32N<\/td>TI\/Nexperia<\/td>Through-hole DIP version of HCT family for prototyping and repair<\/td>DIP-14<\/td>4.5-5.5V TTL-in<\/td><\/tr>\n
        74AC32D<\/td>TI\/Nexperia<\/td>Advanced CMOS with 2-6V supply and higher output drive current (24mA vs 6mA for HC)<\/td>SOIC-14<\/td>2-6V CMOS<\/td><\/tr>\n
        74AC32N<\/td>TI\/Nexperia<\/td>Through-hole DIP version of AC family for prototyping and repair<\/td>DIP-14<\/td>2-6V CMOS<\/td><\/tr>\n
        74LVC32D<\/td>TI\/Nexperia<\/td>Low-voltage CMOS for 1.65-3.6V modern logic with 24mA output drive and bus-hold inputs<\/td>SOIC-14<\/td>1.65-3.6V CMOS<\/td><\/tr>\n
        74LVC32N<\/td>TI\/Nexperia<\/td>Through-hole DIP version of LVC family for prototyping and repair<\/td>DIP-14<\/td>1.65-3.6V CMOS<\/td><\/tr>\n<\/table>\n

        The 7432 is a Quad 2-Input OR Gate. Family variants span from the original LS TTL (5V only) to modern LVC\/AUP (down to 0.8V). HC and HCT versions offer 2-6V CMOS operation with HCT providing TTL-compatible input thresholds for mixed 5V systems. CD4000-series equivalents offer the widest 3-18V supply range at the cost of lower switching speed. DIP packages (N suffix) are through-hole; SOIC (D suffix) and TSSOP are surface-mount.<\/p>"},"_links":{"self":[{"href":"https:\/\/materialparts.com\/zh\/wp-json\/wp\/v2\/posts\/7950","targetHints":{"allow":["GET"]}}],"collection":[{"href":"https:\/\/materialparts.com\/zh\/wp-json\/wp\/v2\/posts"}],"about":[{"href":"https:\/\/materialparts.com\/zh\/wp-json\/wp\/v2\/types\/post"}],"author":[{"embeddable":true,"href":"https:\/\/materialparts.com\/zh\/wp-json\/wp\/v2\/users\/2"}],"replies":[{"embeddable":true,"href":"https:\/\/materialparts.com\/zh\/wp-json\/wp\/v2\/comments?post=7950"}],"version-history":[{"count":1,"href":"https:\/\/materialparts.com\/zh\/wp-json\/wp\/v2\/posts\/7950\/revisions"}],"predecessor-version":[{"id":8176,"href":"https:\/\/materialparts.com\/zh\/wp-json\/wp\/v2\/posts\/7950\/revisions\/8176"}],"wp:attachment":[{"href":"https:\/\/materialparts.com\/zh\/wp-json\/wp\/v2\/media?parent=7950"}],"wp:term":[{"taxonomy":"category","embeddable":true,"href":"https:\/\/materialparts.com\/zh\/wp-json\/wp\/v2\/categories?post=7950"},{"taxonomy":"post_tag","embeddable":true,"href":"https:\/\/materialparts.com\/zh\/wp-json\/wp\/v2\/tags?post=7950"},{"taxonomy":"chip_brand","embeddable":true,"href":"https:\/\/materialparts.com\/zh\/wp-json\/wp\/v2\/chip_brand?post=7950"}],"curies":[{"name":"wp","href":"https:\/\/api.w.org\/{rel}","templated":true}]}}