{"id":7939,"date":"2026-06-28T05:54:09","date_gmt":"2026-06-28T05:54:09","guid":{"rendered":"https:\/\/materialparts.com\/sn74ls373n-2\/"},"modified":"2026-06-28T11:45:39","modified_gmt":"2026-06-28T11:45:39","slug":"sn74ls373n-2","status":"publish","type":"post","link":"https:\/\/materialparts.com\/zh\/sn74ls373n-2\/","title":{"rendered":"SN74LS373N"},"content":{"rendered":"

\u4ea7\u54c1\u6982\u89c8<\/h2>\n

The SN74LS373N from Texas Instruments is an octal transparent D-type latch with 3-state outputs, controlled by a single latch enable and output enable, in a 20-pin PDIP package.<\/p>\n

\u4e3b\u8981\u89c4\u683c<\/h2>\n\n\n\n\n\n\n\n\n\n\n\n
Number of Latches<\/td>\n8 (octal)<\/td>\n<\/tr>\n
\u903b\u8f91\u5bb6\u65cf<\/td>\nLS (Low-power Schottky)<\/td>\n<\/tr>\n
\u7535\u6e90\u7535\u538b<\/td>\n4.75V to 5.25V (5V nominal)<\/td>\n<\/tr>\n
Latch Enable (LE)<\/td>\nTransparent when HIGH, latched when LOW<\/td>\n<\/tr>\n
Output Enable (OE)<\/td>\nActive-low; HIGH = 3-state (high impedance)<\/td>\n<\/tr>\n
\u8f93\u51fa\u7c7b\u578b<\/td>\n3-state (for bus sharing)<\/td>\n<\/tr>\n
\u4f20\u64ad\u5ef6\u8fdf<\/td>\n18ns typical (D to Q, LE=HIGH)<\/td>\n<\/tr>\n
Latch Hold Time<\/td>\n10ns minimum<\/td>\n<\/tr>\n
\u5de5\u4f5c\u6e29\u5ea6<\/td>\n0\u00b0C to +70\u00b0C<\/td>\n<\/tr>\n
\u5305\u88c5<\/td>\nPDIP-20 (24.33 x 6.35mm)<\/td>\n<\/tr>\n<\/table>\n

\u7279\u70b9<\/h2>\n
    \n
  • 8-bit transparent D-type latch<\/li>\n
  • 3-state outputs for bus driving<\/li>\n
  • Single latch enable for all 8 bits<\/li>\n
  • Output enable for bus sharing<\/li>\n
  • 18ns typical propagation delay<\/li>\n
  • Industry-standard 74373 pinout<\/li>\n<\/ul>\n

    \u5e94\u7528<\/h2>\n
      \n
    • Address latch for multiplexed bus<\/li>\n
    • Output port expansion<\/li>\n
    • Data capture and hold<\/li>\n
    • Bus buffering and isolation<\/li>\n
    • Microprocessor I\/O latching<\/li>\n<\/ul>","protected":false},"excerpt":{"rendered":"

      Product Overview The SN74LS373N from Texas Instruments is an octal transparent D-type latch with 3-state outputs, controlled by a single latch enable and output enable, in a 20-pin PDIP package. Key Specifications Number of Latches 8 (octal) Logic Family LS (Low-power Schottky) Supply Voltage 4.75V to 5.25V (5V nominal) Latch Enable (LE) Transparent when HIGH, […]<\/p>\n","protected":false},"author":2,"featured_media":0,"comment_status":"open","ping_status":"","sticky":false,"template":"","format":"standard","meta":{"_acf_changed":false,"footnotes":""},"categories":[13,20],"tags":[],"chip_brand":[138],"class_list":["post-7939","post","type-post","status-publish","format-standard","hentry","category-integrated-circuits-ics","category-interface-ics","chip_brand-ti"],"acf":{"brief_explanation":"Octal transparent latch, 3-state, LE\/OE, PDIP-20","date_code":"","package_case":"PDIP-20 (24.33 x 6.35 x 5.08mm, 2.54mm pitch, through-hole)","in_stock":4800,"datasheet":"https:\/\/www.ti.com\/lit\/ds\/symlink\/sn74ls373.pdf","price":"$0.55 @ 1ku","product_introduction":"The SN74LS373N from Texas Instruments is an octal transparent D-type latch with 3-state outputs, commonly used for address latching on multiplexed address\/data buses such as the Intel 8051 microcontroller. When the latch enable (LE) is HIGH, the eight D inputs pass transparently to the Q outputs. When LE transitions from HIGH to LOW, the current data is latched (held) on the Q outputs, and further changes on D are ignored. The output enable (OE) is active-low; when OE is HIGH, all eight outputs are in the high-impedance state, effectively disconnecting the latch from the bus. When OE is LOW, the latched data appears on the outputs. The transparent mode (LE=HIGH) allows the latch to function as a buffer, while the latched mode (LE=LOW) holds data for downstream circuitry. The 3-state outputs allow multiple 373s to share a common bus. The N suffix denotes the PDIP-20 through-hole package.","working_principle":"The SN74LS373N contains eight identical D-type latches. When the latch enable (LE) is HIGH, each latch is transparent: the Q output follows the D input. When LE goes LOW, each latch captures the D input value present at the LE transition and holds it. While LE is LOW, changes on D do not affect Q. This transparent-then-latch behavior is essential for multiplexed bus systems: the address and data share the same physical bus lines, and the 373 captures the address during the address phase of the bus cycle so that the address remains stable while the data phase uses the same bus lines. The output enable (OE) controls the 3-state output buffers: when OE is LOW, the latched Q values drive the output pins; when OE is HIGH, the outputs are high-impedance (floating), allowing other devices to drive the bus. The 10ns latch hold time means the D input must be stable for at least 10ns after LE goes LOW for reliable latching. In an 8051 system, the ALE (Address Latch Enable) signal connects to LE; ALE goes HIGH during the address phase (allowing address to pass through to the latch) and goes LOW to latch the address before the data phase begins.","pin_description":"\n
      Pin<\/th>Name<\/th>Type<\/th>Description<\/th><\/tr>\n
      1<\/td>OE<\/td>Input<\/td>Output enable (active LOW; HIGH=3-state)<\/td><\/tr>\n
      2<\/td>1Q<\/td>Output<\/td>Latch 1 output (3-state)<\/td><\/tr>\n
      3<\/td>1D<\/td>Input<\/td>Latch 1 data input<\/td><\/tr>\n
      4<\/td>2D<\/td>Input<\/td>Latch 2 data input<\/td><\/tr>\n
      5<\/td>2Q<\/td>Output<\/td>Latch 2 output (3-state)<\/td><\/tr>\n
      6<\/td>3Q<\/td>Output<\/td>Latch 3 output (3-state)<\/td><\/tr>\n
      7<\/td>3D<\/td>Input<\/td>Latch 3 data input<\/td><\/tr>\n
      8<\/td>4D<\/td>Input<\/td>Latch 4 data input<\/td><\/tr>\n
      9<\/td>4Q<\/td>Output<\/td>Latch 4 output (3-state)<\/td><\/tr>\n
      10<\/td>GND<\/td>Power<\/td>Ground<\/td><\/tr>\n
      11<\/td>LE<\/td>Input<\/td>Latch enable (HIGH=transparent, LOW=latched)<\/td><\/tr>\n
      12<\/td>5Q<\/td>Output<\/td>Latch 5 output (3-state)<\/td><\/tr>\n
      13<\/td>5D<\/td>Input<\/td>Latch 5 data input<\/td><\/tr>\n
      14<\/td>6D<\/td>Input<\/td>Latch 6 data input<\/td><\/tr>\n
      15<\/td>6Q<\/td>Output<\/td>Latch 6 output (3-state)<\/td><\/tr>\n
      16<\/td>7Q<\/td>Output<\/td>Latch 7 output (3-state)<\/td><\/tr>\n
      17<\/td>7D<\/td>Input<\/td>Latch 7 data input<\/td><\/tr>\n
      18<\/td>8D<\/td>Input<\/td>Latch 8 data input<\/td><\/tr>\n
      19<\/td>8Q<\/td>Output<\/td>Latch 8 output (3-state)<\/td><\/tr>\n
      20<\/td>VCC<\/td>Power<\/td>Supply (4.75V to 5.25V)<\/td><\/tr>\n<\/table>","application_scenarios":"
        \n
      • 8051 Address Latch:<\/strong> AD0-AD7 \u2192 D0-D7; ALE \u2192 LE; Q0-Q7 \u2192 address bus; latches address when ALE falls<\/li>\n
      • Output Port:<\/strong> D from data bus; LE from \/WR + \/CS; OE always LOW; latched outputs drive peripherals<\/li>\n
      • Input Capture:<\/strong> External data \u2192 D; LE from control signal; captures snapshot of 8-bit data on LE falling edge<\/li>\n
      • Bus Isolation:<\/strong> OE controlled by system; disconnects latch from bus when not addressed; multiple 373s share one bus<\/li>\n
      • Pipeline Stage:<\/strong> LE from system clock; captures data on one phase, holds for next; 8-bit pipeline register<\/li>\n<\/ul>","alternative_models":"\n
        Model<\/th>Manufacturer<\/th>Key Difference<\/th>Package<\/th>Supply<\/th><\/tr>\n
        74LS373N<\/td>TI\/Nexperia<\/td>Original TTL version with 5V-only supply, typical propagation delay 10-15ns<\/td>DIP-20<\/td>5V TTL<\/td><\/tr>\n
        74LS373D<\/td>TI\/Nexperia<\/td>Surface-mount SOIC version of LS with identical logic function<\/td>SOIC-20<\/td>5V TTL<\/td><\/tr>\n
        74HC373D<\/td>TI\/Nexperia<\/td>CMOS version with wide 2-6V supply range, lower power consumption and higher noise immunity<\/td>SOIC-20<\/td>2-6V CMOS<\/td><\/tr>\n
        74HC373N<\/td>TI\/Nexperia<\/td>Through-hole DIP version of HC family for prototyping and repair<\/td>DIP-20<\/td>2-6V CMOS<\/td><\/tr>\n
        74HCT373D<\/td>TI\/Nexperia<\/td>CMOS with TTL-compatible input levels, ideal for mixing with LS devices at 5V<\/td>SOIC-20<\/td>4.5-5.5V TTL-in<\/td><\/tr>\n
        74HCT373N<\/td>TI\/Nexperia<\/td>Through-hole DIP version of HCT family for prototyping and repair<\/td>DIP-20<\/td>4.5-5.5V TTL-in<\/td><\/tr>\n
        74LVC373D<\/td>TI\/Nexperia<\/td>Low-voltage CMOS for 1.65-3.6V modern logic with 24mA output drive and bus-hold inputs<\/td>SOIC-20<\/td>1.65-3.6V CMOS<\/td><\/tr>\n
        74LVC373N<\/td>TI\/Nexperia<\/td>Through-hole DIP version of LVC family for prototyping and repair<\/td>DIP-20<\/td>1.65-3.6V CMOS<\/td><\/tr>\n<\/table>\n

        The 74373 is a Octal Transparent Latch with 3-State Output. Family variants span from the original LS TTL (5V only) to modern LVC\/AUP (down to 0.8V). HC and HCT versions offer 2-6V CMOS operation with HCT providing TTL-compatible input thresholds for mixed 5V systems. CD4000-series equivalents offer the widest 3-18V supply range at the cost of lower switching speed. DIP packages (N suffix) are through-hole; SOIC (D suffix) and TSSOP are surface-mount.<\/p>"},"_links":{"self":[{"href":"https:\/\/materialparts.com\/zh\/wp-json\/wp\/v2\/posts\/7939","targetHints":{"allow":["GET"]}}],"collection":[{"href":"https:\/\/materialparts.com\/zh\/wp-json\/wp\/v2\/posts"}],"about":[{"href":"https:\/\/materialparts.com\/zh\/wp-json\/wp\/v2\/types\/post"}],"author":[{"embeddable":true,"href":"https:\/\/materialparts.com\/zh\/wp-json\/wp\/v2\/users\/2"}],"replies":[{"embeddable":true,"href":"https:\/\/materialparts.com\/zh\/wp-json\/wp\/v2\/comments?post=7939"}],"version-history":[{"count":1,"href":"https:\/\/materialparts.com\/zh\/wp-json\/wp\/v2\/posts\/7939\/revisions"}],"predecessor-version":[{"id":8180,"href":"https:\/\/materialparts.com\/zh\/wp-json\/wp\/v2\/posts\/7939\/revisions\/8180"}],"wp:attachment":[{"href":"https:\/\/materialparts.com\/zh\/wp-json\/wp\/v2\/media?parent=7939"}],"wp:term":[{"taxonomy":"category","embeddable":true,"href":"https:\/\/materialparts.com\/zh\/wp-json\/wp\/v2\/categories?post=7939"},{"taxonomy":"post_tag","embeddable":true,"href":"https:\/\/materialparts.com\/zh\/wp-json\/wp\/v2\/tags?post=7939"},{"taxonomy":"chip_brand","embeddable":true,"href":"https:\/\/materialparts.com\/zh\/wp-json\/wp\/v2\/chip_brand?post=7939"}],"curies":[{"name":"wp","href":"https:\/\/api.w.org\/{rel}","templated":true}]}}