{"id":7936,"date":"2026-06-28T05:54:05","date_gmt":"2026-06-28T05:54:05","guid":{"rendered":"https:\/\/materialparts.com\/sn74ls74an-2\/"},"modified":"2026-06-28T11:45:43","modified_gmt":"2026-06-28T11:45:43","slug":"sn74ls74an-2","status":"publish","type":"post","link":"https:\/\/materialparts.com\/zh\/sn74ls74an-2\/","title":{"rendered":"SN74LS74AN"},"content":{"rendered":"

\u4ea7\u54c1\u6982\u89c8<\/h2>\n

The SN74LS74AN from Texas Instruments is a dual D-type positive-edge-triggered flip-flop with preset and clear inputs, complementary outputs, and 25MHz maximum clock frequency in a 14-pin PDIP package.<\/p>\n

\u4e3b\u8981\u89c4\u683c<\/h2>\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n
Number of Flip-Flops<\/td>\n2 (dual D-type)<\/td>\n<\/tr>\n
\u903b\u8f91\u5bb6\u65cf<\/td>\nLS (Low-power Schottky)<\/td>\n<\/tr>\n
\u7535\u6e90\u7535\u538b<\/td>\n4.75V to 5.25V (5V nominal)<\/td>\n<\/tr>\n
Trigger Type<\/td>\nPositive-edge triggered<\/td>\n<\/tr>\n
Outputs<\/td>\nTrue (Q) and complementary (Q\u0305) per flip-flop<\/td>\n<\/tr>\n
Preset (PRE)<\/td>\nActive-low, asynchronous (sets Q=HIGH)<\/td>\n<\/tr>\n
Clear (CLR)<\/td>\nActive-low, asynchronous (sets Q=LOW)<\/td>\n<\/tr>\n
Maximum Clock Frequency<\/td>\n25MHz typical<\/td>\n<\/tr>\n
Propagation Delay (CLK to Q)<\/td>\n25ns typical<\/td>\n<\/tr>\n
Setup Time<\/td>\n15ns minimum before clock edge<\/td>\n<\/tr>\n
Hold Time<\/td>\n0ns minimum after clock edge<\/td>\n<\/tr>\n
\u5de5\u4f5c\u6e29\u5ea6<\/td>\n0\u00b0C to +70\u00b0C<\/td>\n<\/tr>\n
\u5305\u88c5<\/td>\nPDIP-14 (19.3 x 6.35mm)<\/td>\n<\/tr>\n<\/table>\n

\u7279\u70b9<\/h2>\n
    \n
  • Dual D-type positive-edge-triggered flip-flops<\/li>\n
  • Independent preset and clear per flip-flop<\/li>\n
  • Complementary outputs (Q and Q\u0305)<\/li>\n
  • Asynchronous preset (sets Q=HIGH)<\/li>\n
  • Asynchronous clear (sets Q=LOW)<\/li>\n
  • 25MHz maximum clock frequency<\/li>\n<\/ul>\n

    \u5e94\u7528<\/h2>\n
      \n
    • Frequency division (\u00f72)<\/li>\n
    • Data synchronization<\/li>\n
    • One-shot pulse generation<\/li>\n
    • Switch debouncing<\/li>\n
    • Digital delay and pipelining<\/li>\n<\/ul>","protected":false},"excerpt":{"rendered":"

      Product Overview The SN74LS74AN from Texas Instruments is a dual D-type positive-edge-triggered flip-flop with preset and clear inputs, complementary outputs, and 25MHz maximum clock frequency in a 14-pin PDIP package. Key Specifications Number of Flip-Flops 2 (dual D-type) Logic Family LS (Low-power Schottky) Supply Voltage 4.75V to 5.25V (5V nominal) Trigger Type Positive-edge triggered Outputs […]<\/p>\n","protected":false},"author":2,"featured_media":0,"comment_status":"open","ping_status":"","sticky":false,"template":"","format":"standard","meta":{"_acf_changed":false,"footnotes":""},"categories":[13,20],"tags":[],"chip_brand":[138],"class_list":["post-7936","post","type-post","status-publish","format-standard","hentry","category-integrated-circuits-ics","category-interface-ics","chip_brand-ti"],"acf":{"brief_explanation":"Dual D flip-flop, edge-triggered, PRE\/CLR, Q+Q\u0305, 25MHz, PDIP-14","date_code":"","package_case":"PDIP-14 (19.3 x 6.35 x 4.57mm, 2.54mm pitch, through-hole)","in_stock":7500,"datasheet":"https:\/\/www.ti.com\/lit\/ds\/symlink\/sn74ls74a.pdf","price":"$0.38 @ 1ku","product_introduction":"The SN74LS74AN from Texas Instruments contains two independent D-type positive-edge-triggered flip-flops, each with asynchronous preset (PRE) and clear (CLR) inputs and complementary Q\/Q\u0305 outputs. The 74LS74 is the most widely-used D flip-flop in TTL design. On the rising edge of the clock (CLK), the D input is transferred to the Q output. The asynchronous PRE input, when LOW, immediately sets Q=HIGH regardless of CLK or D. The asynchronous CLR input, when LOW, immediately sets Q=LOW. Both PRE and CLR override the clock. The complementary Q\u0305 output provides the inverted Q value without additional logic. For frequency division, connecting Q\u0305 to D creates a toggle flip-flop that divides the clock frequency by 2. The A suffix denotes the improved LS version. The N suffix denotes the PDIP-14 through-hole package.","working_principle":"Each D-type flip-flop in the SN74LS74AN captures the logic level at its D input on the rising edge of CLK. The captured value appears at Q, and the inverted value at Q\u0305. Between clock edges, the outputs hold their values. The asynchronous PRE (preset) input, when LOW, forces Q=HIGH and Q\u0305=LOW regardless of CLK or D. The asynchronous CLR (clear) input, when LOW, forces Q=LOW and Q\u0305=HIGH. Both PRE and CLR are active-low and override the synchronous (clocked) operation. If both PRE and CLR are simultaneously LOW, both Q and Q\u0305 go HIGH (invalid state); the state that results when both return HIGH is indeterminate, so this condition should be avoided. For a toggle (\u00f72) configuration, Q\u0305 connects to D. Each rising clock edge captures the opposite of the current Q value, causing Q to toggle: 0\u21921\u21920\u21921... The output frequency is half the clock frequency. For a one-shot (monostable) pulse, D is held HIGH, and a brief LOW pulse on CLR clears Q; when CLR returns HIGH, the next clock edge captures D=HIGH, setting Q=HIGH for one clock period.","pin_description":"\n
      Pin<\/th>Name<\/th>Type<\/th>Description<\/th><\/tr>\n
      1<\/td>1CLR<\/td>Input<\/td>Flip-flop 1 clear (active LOW, async)<\/td><\/tr>\n
      2<\/td>1D<\/td>Input<\/td>Flip-flop 1 data input<\/td><\/tr>\n
      3<\/td>1CLK<\/td>Input<\/td>Flip-flop 1 clock (rising edge triggered)<\/td><\/tr>\n
      4<\/td>1PRE<\/td>Input<\/td>Flip-flop 1 preset (active LOW, async)<\/td><\/tr>\n
      5<\/td>1Q<\/td>Output<\/td>Flip-flop 1 true output<\/td><\/tr>\n
      6<\/td>1Q\u0305<\/td>Output<\/td>Flip-flop 1 complementary output<\/td><\/tr>\n
      7<\/td>GND<\/td>Power<\/td>Ground<\/td><\/tr>\n
      8<\/td>2Q\u0305<\/td>Output<\/td>Flip-flop 2 complementary output<\/td><\/tr>\n
      9<\/td>2Q<\/td>Output<\/td>Flip-flop 2 true output<\/td><\/tr>\n
      10<\/td>2PRE<\/td>Input<\/td>Flip-flop 2 preset (active LOW, async)<\/td><\/tr>\n
      11<\/td>2CLK<\/td>Input<\/td>Flip-flop 2 clock (rising edge triggered)<\/td><\/tr>\n
      12<\/td>2D<\/td>Input<\/td>Flip-flop 2 data input<\/td><\/tr>\n
      13<\/td>2CLR<\/td>Input<\/td>Flip-flop 2 clear (active LOW, async)<\/td><\/tr>\n
      14<\/td>VCC<\/td>Power<\/td>Supply (4.75V to 5.25V)<\/td><\/tr>\n<\/table>","application_scenarios":"
        \n
      • \u00f72 Divider:<\/strong> Q\u0305 to D; CLK input; Q output = half frequency; cascade for \u00f74, \u00f78, etc.<\/li>\n
      • Data Sync:<\/strong> Asynchronous input \u2192 D; system clock \u2192 CLK; Q output synchronized to clock edge<\/li>\n
      • One-Shot:<\/strong> D=HIGH; trigger on CLR; Q goes HIGH on next clock for exactly one clock period<\/li>\n
      • Debounce:<\/strong> Switch through RC filter \u2192 D; clock at 100Hz; samples clean state after bounce settles<\/li>\n
      • Shift Register:<\/strong> Chain of 74LS74 flip-flops; D of each from Q of previous; shifts data one bit per clock<\/li>\n<\/ul>","alternative_models":"\n
        Model<\/th>Manufacturer<\/th>Key Difference<\/th>Package<\/th>Supply<\/th><\/tr>\n
        74LS74N<\/td>TI\/Nexperia<\/td>Original TTL version with 5V-only supply, typical propagation delay 10-15ns<\/td>DIP-14<\/td>5V TTL<\/td><\/tr>\n
        74LS74D<\/td>TI\/Nexperia<\/td>Surface-mount SOIC version of LS with identical logic function<\/td>SOIC-14<\/td>5V TTL<\/td><\/tr>\n
        74HC74D<\/td>TI\/Nexperia<\/td>CMOS version with wide 2-6V supply range, lower power consumption and higher noise immunity<\/td>SOIC-14<\/td>2-6V CMOS<\/td><\/tr>\n
        74HC74N<\/td>TI\/Nexperia<\/td>Through-hole DIP version of HC family for prototyping and repair<\/td>DIP-14<\/td>2-6V CMOS<\/td><\/tr>\n
        74HCT74D<\/td>TI\/Nexperia<\/td>CMOS with TTL-compatible input levels, ideal for mixing with LS devices at 5V<\/td>SOIC-14<\/td>4.5-5.5V TTL-in<\/td><\/tr>\n
        74HCT74N<\/td>TI\/Nexperia<\/td>Through-hole DIP version of HCT family for prototyping and repair<\/td>DIP-14<\/td>4.5-5.5V TTL-in<\/td><\/tr>\n
        74AC74D<\/td>TI\/Nexperia<\/td>Advanced CMOS with 2-6V supply and higher output drive current (24mA vs 6mA for HC)<\/td>SOIC-14<\/td>2-6V CMOS<\/td><\/tr>\n
        74AC74N<\/td>TI\/Nexperia<\/td>Through-hole DIP version of AC family for prototyping and repair<\/td>DIP-14<\/td>2-6V CMOS<\/td><\/tr>\n
        74LVC74D<\/td>TI\/Nexperia<\/td>Low-voltage CMOS for 1.65-3.6V modern logic with 24mA output drive and bus-hold inputs<\/td>SOIC-14<\/td>1.65-3.6V CMOS<\/td><\/tr>\n
        74LVC74N<\/td>TI\/Nexperia<\/td>Through-hole DIP version of LVC family for prototyping and repair<\/td>DIP-14<\/td>1.65-3.6V CMOS<\/td><\/tr>\n<\/table>\n

        The 7474 is a Dual D-Type Positive-Edge-Triggered Flip-Flop. Family variants span from the original LS TTL (5V only) to modern LVC\/AUP (down to 0.8V). HC and HCT versions offer 2-6V CMOS operation with HCT providing TTL-compatible input thresholds for mixed 5V systems. CD4000-series equivalents offer the widest 3-18V supply range at the cost of lower switching speed. DIP packages (N suffix) are through-hole; SOIC (D suffix) and TSSOP are surface-mount.<\/p>"},"_links":{"self":[{"href":"https:\/\/materialparts.com\/zh\/wp-json\/wp\/v2\/posts\/7936","targetHints":{"allow":["GET"]}}],"collection":[{"href":"https:\/\/materialparts.com\/zh\/wp-json\/wp\/v2\/posts"}],"about":[{"href":"https:\/\/materialparts.com\/zh\/wp-json\/wp\/v2\/types\/post"}],"author":[{"embeddable":true,"href":"https:\/\/materialparts.com\/zh\/wp-json\/wp\/v2\/users\/2"}],"replies":[{"embeddable":true,"href":"https:\/\/materialparts.com\/zh\/wp-json\/wp\/v2\/comments?post=7936"}],"version-history":[{"count":1,"href":"https:\/\/materialparts.com\/zh\/wp-json\/wp\/v2\/posts\/7936\/revisions"}],"predecessor-version":[{"id":8182,"href":"https:\/\/materialparts.com\/zh\/wp-json\/wp\/v2\/posts\/7936\/revisions\/8182"}],"wp:attachment":[{"href":"https:\/\/materialparts.com\/zh\/wp-json\/wp\/v2\/media?parent=7936"}],"wp:term":[{"taxonomy":"category","embeddable":true,"href":"https:\/\/materialparts.com\/zh\/wp-json\/wp\/v2\/categories?post=7936"},{"taxonomy":"post_tag","embeddable":true,"href":"https:\/\/materialparts.com\/zh\/wp-json\/wp\/v2\/tags?post=7936"},{"taxonomy":"chip_brand","embeddable":true,"href":"https:\/\/materialparts.com\/zh\/wp-json\/wp\/v2\/chip_brand?post=7936"}],"curies":[{"name":"wp","href":"https:\/\/api.w.org\/{rel}","templated":true}]}}